From: lkcl <lkcl@web>
Date: Thu, 18 Mar 2021 12:18:30 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~1179
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=da4380013677c9d3d81dbc4bc4ff73e2f3300552;p=libreriscv.git

---

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 0f54ff3bd..893722e87 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -22,6 +22,7 @@ Links:
 * <https://bugs.libre-soc.org/show_bug.cgi?id=615> agree sv assembly syntax
 * <https://bugs.libre-soc.org/show_bug.cgi?id=617> TestIssuer add single/twin Predication
 * <https://bugs.libre-soc.org/show_bug.cgi?id=618> ISACaller add single/twin Predication
+* <https://bugs.libre-soc.org/show_bug.cgi?id=619> tracking manual augmentation of CSV files
 
 # Code to convert