From: lkcl Date: Fri, 21 Apr 2023 14:14:19 +0000 (+0100) Subject: (no commit message) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=da59343de1423fc59d0b6865c1aa52a1e6c34ab3;p=libreriscv.git --- diff --git a/openpower/sv/rfc/ls011.mdwn b/openpower/sv/rfc/ls011.mdwn index 4cb05c3e9..0c63d3a8e 100644 --- a/openpower/sv/rfc/ls011.mdwn +++ b/openpower/sv/rfc/ls011.mdwn @@ -303,4 +303,144 @@ Special Registers Altered: \newpage{} +# Fixed-Point Store Post-Update + +Add the following as a new section in Fixed-Point Store, Book I + +## Store Byte with Update + +D-Form + +* stbup RS,D(RA) + +Pseudo-code: + + EA <- (RA) + EXTS(D) + ea <- (RA) + MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1] + RA <- EA + +Special Registers Altered: + + None + +## Store Byte with Update Indexed + +X-Form + +* stbupx RS,RA,RB + +Pseudo-code: + + EA <- (RA) + (RB) + ea <- (RA) + MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1] + RA <- EA + +Special Registers Altered: + + None + +## Store Halfword with Update + +D-Form + +* sthup RS,D(RA) + +Pseudo-code: + + EA <- (RA) + EXTS(D) + ea <- (RA) + MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1] + RA <- EA + +Special Registers Altered: + + None + +## Store Halfword with Update Indexed + +X-Form + +* sthupx RS,RA,RB + +Pseudo-code: + + EA <- (RA) + (RB) + ea <- (RA) + MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1] + RA <- EA + +Special Registers Altered: + + None + +## Store Word with Update + +D-Form + +* stwup RS,D(RA) + +Pseudo-code: + + EA <- (RA) + EXTS(D) + ea <- (RA) + MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1] + RA <- EA + +Special Registers Altered: + + None + +## Store Word with Update Indexed + +X-Form + +* stwupx RS,RA,RB + +Pseudo-code: + + EA <- (RA) + (RB) + ea <- (RA) + MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1] + RA <- EA + +Special Registers Altered: + + None + +## Store Doubleword with Update + +DS-Form + +* stdup RS,DS(RA) + +Pseudo-code: + + EA <- (RA) + EXTS(DS || 0b00) + ea <- (RA) + MEM(ea, 8) <- (RS) + RA <- EA + +Special Registers Altered: + + None + +## Store Doubleword with Update Indexed + +X-Form + +* stdupx RS,RA,RB + +Pseudo-code: + + EA <- (RA) + (RB) + ea <- (RA) + MEM(ea, 8) <- (RS) + RA <- EA + +Special Registers Altered: + + None + [[!tag opf_rfc]]