From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 28 Jun 2019 17:59:03 +0000 (-0700)
Subject: Merge pull request #1098 from YosysHQ/xaig
X-Git-Tag: working-ls180~1237
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=da5f83039527bf50af001671744f351988c3261a;p=yosys.git

Merge pull request #1098 from YosysHQ/xaig

"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
---

da5f83039527bf50af001671744f351988c3261a
diff --cc Makefile
index 5ec3e0312,6c5a436c1..d33f27b63
--- a/Makefile
+++ b/Makefile
@@@ -686,8 -680,9 +686,9 @@@ test: $(TARGETS) $(EXTRA_TARGETS
  	+cd tests/sat && bash run-test.sh
  	+cd tests/svinterfaces && bash run-test.sh $(SEEDOPT)
  	+cd tests/opt && bash run-test.sh
 -	+cd tests/aiger && bash run-test.sh
 +	+cd tests/aiger && bash run-test.sh $(ABCOPT)
  	+cd tests/arch && bash run-test.sh
+ 	+cd tests/simple_abc9 && bash run-test.sh $(SEEDOPT)
  	@echo ""
  	@echo "  Passed \"make test\"."
  	@echo ""