From: lkcl <lkcl@web>
Date: Thu, 7 Jan 2021 15:24:12 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~587
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=da6705ca17ffe485bf9b53362d4bcc6b2dff4349;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 43afa7e87..085a7b298 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -127,7 +127,8 @@ Note the following:
 * `svctx` specifies the SV Context and includes VL as well as source and
   destination elwidth overrides.
 
-Below is the pseudocode for Unit-Strided LD (which includes Vector capability):
+Below is the pseudocode for Unit-Strided LD (which includes Vector capability).  Note that twin predication, predication-zeroing, saturation
+and other modes have all been removed, for clarity and simplicity:
 
     # LD not VLD! (ldbrx if brev=True)
     # this covers unit stride mode