From: lkcl Date: Fri, 6 May 2022 08:49:51 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~2400 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=da677a1756bf506dbe92b6c701490673f88ca5c5;p=libreriscv.git --- diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index e54dfcf16..177e30d91 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -12,12 +12,13 @@ Inventing a new Scalar ISA from scratch is over a decade-long task including simulators and compilers: OpenRISC 1200 took 12 years to -mature. A Vector or Packed SIMD ISA to reach stable general-purpose +mature. A Vector or Packed SIMD ISA to reach stable *general-purpose* auto-vectorisation compiler support has never been achieved in the history of computing, not with the combined resources of ARM, Intel, AMD, MIPS, Sun Microsystems, SGI, Cray, and many more. Rather: GPUs -have ultra-specialist compilers that are designed from the ground up -to support Vector/SIMD parallelism, and associated standards managed by +have ultra-specialist compilers (CUDA) that are designed from the ground up +to support Vector/SIMD parallelism, and associated standards +(SPIR-V, Vulkan, OpenCL) managed by the Khronos Group, with multi-man-century development committment from multiple billion-dollar-revenue companies, to sustain them.