From: Luke Kenneth Casson Leighton Date: Tue, 24 Apr 2018 09:03:44 +0000 (+0100) Subject: shuffle X-Git-Tag: convert-csv-opcode-to-binary~5586 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=da6aa26f100622f5453a2c5b7f98cb8ab248783c;p=libreriscv.git shuffle --- diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn index 1ae1dfce3..2f2bce985 100644 --- a/simple_v_extension.mdwn +++ b/simple_v_extension.mdwn @@ -346,6 +346,190 @@ instructions to deal with corner-cases is thus avoided, and implementors get to choose precisely where to focus and target the benefits of their implementation efforts, without "extra baggage". +# CSRs + +There are a number of CSRs needed, which are used at the instruction +decode phase to re-interpret standard RV opcodes (a practice that has +precedent in the setting of MISA to enable / disable extensions). + +* Integer Register N is Vector of length M: r(N) -> r(N..N+M-1) +* Integer Register N is of implicit bitwidth M (M=default,8,16,32,64) +* Floating-point Register N is Vector of length M: r(N) -> r(N..N+M-1) +* Floating-point Register N is of implicit bitwidth M (M=default,8,16,32,64) +* Integer Register N is a Predication Register (note: a key-value store) +* Vector Length CSR (VSETVL, VGETVL) + +Notes: + +* for the purposes of LOAD / STORE, Integer Registers which are + marked as a Vector will result in a Vector LOAD / STORE. +* Vector Lengths are *not* the same as vsetl but are an integral part + of vsetl. +* Actual vector length is *multipled* by how many blocks of length + "bitwidth" may fit into an XLEN-sized register file. +* Predication is a key-value store due to the implicit referencing, + as opposed to having the predicate register explicitly in the instruction. + +## Predication CSR + +The Predication CSR is a key-value store indicating whether, if a given +destination register (integer or floating-point) is referred to in an +instruction, it is to be predicated. The first entry is whether predication +is enabled. The second entry is whether the register index refers to a +floating-point or an integer register. The third entry is the index +of that register which is to be predicated (if referred to). The fourth entry +is the integer register that is treated as a bitfield, indexable by the +vector element index. + +| RegNo | 6 | 5 | (4..0) | (4..0) | +| ----- | - | - | ------- | ------- | +| r0 | pren0 | i/f | regidx | predidx | +| r1 | pren1 | i/f | regidx | predidx | +| .. | pren.. | i/f | regidx | predidx | +| r15 | pren15 | i/f | regidx | predidx | + +The Predication CSR Table is a key-value store, so implementation-wise +it will be faster to turn the table around (maintain topologically +equivalent state): + + fp_pred_enabled[32]; + int_pred_enabled[32]; + for (i = 0; i < 16; i++) + if CSRpred[i].pren: + idx = CSRpred[i].regidx + predidx = CSRpred[i].predidx + if CSRpred[i].type == 0: # integer + int_pred_enabled[idx] = 1 + int_pred_reg[idx] = predidx + else: + fp_pred_enabled[idx] = 1 + fp_pred_reg[idx] = predidx + +So when an operation is to be predicated, it is the internal state that +is used. In Section 6.4.2 of Hwacha's Manual (EECS-2015-262) the following +pseudo-code for operations is given, where p is the explicit (direct) +reference to the predication register to be used: + + for (int i=0; i - -There are a number of CSRs needed, which are used at the instruction -decode phase to re-interpret standard RV opcodes (a practice that has -precedent in the setting of MISA to enable / disable extensions). - -* Integer Register N is Vector of length M: r(N) -> r(N..N+M-1) -* Integer Register N is of implicit bitwidth M (M=default,8,16,32,64) -* Floating-point Register N is Vector of length M: r(N) -> r(N..N+M-1) -* Floating-point Register N is of implicit bitwidth M (M=default,8,16,32,64) -* Integer Register N is a Predication Register (note: a key-value store) -* Vector Length CSR (VSETVL, VGETVL) - -Notes: - -* for the purposes of LOAD / STORE, Integer Registers which are - marked as a Vector will result in a Vector LOAD / STORE. -* Vector Lengths are *not* the same as vsetl but are an integral part - of vsetl. -* Actual vector length is *multipled* by how many blocks of length - "bitwidth" may fit into an XLEN-sized register file. -* Predication is a key-value store due to the implicit referencing, - as opposed to having the predicate register explicitly in the instruction. - -## Predication CSR - -The Predication CSR is a key-value store indicating whether, if a given -destination register (integer or floating-point) is referred to in an -instruction, it is to be predicated. The first entry is whether predication -is enabled. The second entry is whether the register index refers to a -floating-point or an integer register. The third entry is the index -of that register which is to be predicated (if referred to). The fourth entry -is the integer register that is treated as a bitfield, indexable by the -vector element index. - -| RegNo | 6 | 5 | (4..0) | (4..0) | -| ----- | - | - | ------- | ------- | -| r0 | pren0 | i/f | regidx | predidx | -| r1 | pren1 | i/f | regidx | predidx | -| .. | pren.. | i/f | regidx | predidx | -| r15 | pren15 | i/f | regidx | predidx | - -The Predication CSR Table is a key-value store, so implementation-wise -it will be faster to turn the table around (maintain topologically -equivalent state): - - fp_pred_enabled[32]; - int_pred_enabled[32]; - for (i = 0; i < 16; i++) - if CSRpred[i].pren: - idx = CSRpred[i].regidx - predidx = CSRpred[i].predidx - if CSRpred[i].type == 0: # integer - int_pred_enabled[idx] = 1 - int_pred_reg[idx] = predidx - else: - fp_pred_enabled[idx] = 1 - fp_pred_reg[idx] = predidx - -So when an operation is to be predicated, it is the internal state that -is used. In Section 6.4.2 of Hwacha's Manual (EECS-2015-262) the following -pseudo-code for operations is given, where p is the explicit (direct) -reference to the predication register to be used: - - for (int i=0; i What does an ADD of two different-sized vectors do in simple-V?