From: Luke Kenneth Casson Leighton Date: Wed, 12 Jan 2022 11:22:24 +0000 (+0000) Subject: fix issue with priv_mode not being passed correctly to MMU X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=da744a15dc07e13ecac5ca539912111572a0da7b;p=soc.git fix issue with priv_mode not being passed correctly to MMU on instruction load --- diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py index 081ff019..6283f8ac 100644 --- a/src/soc/fu/ldst/loadstore.py +++ b/src/soc/fu/ldst/loadstore.py @@ -123,6 +123,7 @@ class LoadStore1(PortInterfaceBase): self.state = Signal(State) self.instr_fault = Signal() # indicator to request i-cache MMU lookup self.r_instr_fault = Signal() # accessed in external_busy + self.priv_mode = Signal() # only for instruction fetch (not LDST) self.align_intr = Signal() self.busy = Signal() self.wait_dcache = Signal() @@ -445,8 +446,10 @@ class LoadStore1(PortInterfaceBase): m.d.comb += m_out.valid.eq(mmureq) m.d.comb += m_out.iside.eq(self.instr_fault) m.d.comb += m_out.load.eq(ldst_r.load) - m.d.comb += m_out.priv.eq(ldst_r.priv_mode) - # m_out.priv <= r.priv_mode; TODO + with m.If(self.instr_fault): + m.d.comb += m_out.priv.eq(self.priv_mode) + with m.Else(): + m.d.comb += m_out.priv.eq(ldst_r.priv_mode) m.d.comb += m_out.tlbie.eq(self.tlbie) # m_out.mtspr <= mmu_mtspr; # TODO # m_out.sprn <= sprn; # TODO diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py index c1d4d74f..24be3f54 100644 --- a/src/soc/fu/mmu/fsm.py +++ b/src/soc/fu/mmu/fsm.py @@ -225,6 +225,7 @@ class FSMMMUStage(ControlBase): # from accepting any other LD/ST requests. comb += valid.eq(1) # start "pulse" comb += ldst.instr_fault.eq(blip) + comb += ldst.priv_mode.eq(~msr_i[MSR.PR]) comb += ldst.maddr.eq(cia_i) # XXX should not access this! comb += done.eq(ldst.done)