From: Gabe Black <gblack@eecs.umich.edu>
Date: Mon, 30 Jul 2007 20:25:00 +0000 (-0700)
Subject: Make the register indices use the appropriate "fold" bit.
X-Git-Tag: m5_2.0_beta4~243
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=da84aa95a99ef84ff10b7ce53156825e73d0b8e5;p=gem5.git

Make the register indices use the appropriate "fold" bit.

--HG--
extra : convert_revision : 89e15e2ef1f709f2c09238b78f94505ce8ef146d
---

diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 406c74a1f..127e1b98a 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -96,13 +96,13 @@ def operand_types {{
 }};
 
 def operands {{
-        'DestReg':       ('IntReg', 'uqw', 'dest', 'IsInteger', 1),
-        'SrcReg1':       ('IntReg', 'uqw', 'src1', 'IsInteger', 2),
-        'SrcReg2':       ('IntReg', 'uqw', 'src2', 'IsInteger', 3),
-        'Base':          ('IntReg', 'uqw', 'base', 'IsInteger', 4),
-        'Index':         ('IntReg', 'uqw', 'index', 'IsInteger', 5),
-        'Data':          ('IntReg', 'uqw', 'data', 'IsInteger', 6),
-        'rax':           ('IntReg', 'uqw', 'INTREG_RAX', 'IsInteger', 7),
+        'SrcReg1':       ('IntReg', 'uqw', '(((src1 & 0xC) == 4 ? foldOBit : 0) | src1)', 'IsInteger', 1),
+        'SrcReg2':       ('IntReg', 'uqw', '(((src2 & 0xC) == 4 ? foldOBit : 0) | src2)', 'IsInteger', 2),
+        'Base':          ('IntReg', 'uqw', '(((base & 0xC) == 4 ? foldABit : 0) | base)', 'IsInteger', 3),
+        'Index':         ('IntReg', 'uqw', '(((index & 0xC) == 4 ? foldABit : 0) | index)', 'IsInteger', 4),
+        'DestReg':       ('IntReg', 'uqw', '(((dest & 0xC) == 4 ? foldOBit : 0) | dest)', 'IsInteger', 5),
+        'Data':          ('IntReg', 'uqw', '(((data & 0xC) == 4 ? foldOBit : 0) | data)', 'IsInteger', 6),
+        'rax':           ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 7),
         'RIP':           ('NPC', 'uqw', None, (None, None, 'IsControl'), 10),
         'ccFlagBits':       ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20),
         'Mem':           ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
diff --git a/src/arch/x86/regfile.cc b/src/arch/x86/regfile.cc
index f54f531e2..96283cada 100644
--- a/src/arch/x86/regfile.cc
+++ b/src/arch/x86/regfile.cc
@@ -86,6 +86,7 @@
  */
 
 #include "arch/x86/regfile.hh"
+#include "base/trace.hh"
 #include "sim/serialize.hh"
 #include "cpu/thread_context.hh"
 
@@ -209,8 +210,12 @@ void RegFile::setIntReg(int intReg, const IntReg &val)
 
 int X86ISA::flattenIntIndex(ThreadContext * tc, int reg)
 {
-    //For right now, don't do any flattening
-    return reg;
+    //If we need to fold over the index to match byte semantics, do that.
+    //Otherwise, just strip off any extra bits and pass it through.
+    if (reg & (1 << 6))
+        return (reg & ~(1 << 6) - 0x4);
+    else
+        return (reg & ~(1 << 6));
 }
 
 void RegFile::serialize(std::ostream &os)