From: Andreas Hansson <andreas.hansson@arm.com>
Date: Tue, 19 Feb 2013 17:57:47 +0000 (-0500)
Subject: mem: Fix sender state bug and delay popping
X-Git-Tag: stable_2013_06_16~84
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=da950caed24f7674be4aa999c2f17c520165fd84;p=gem5.git

mem: Fix sender state bug and delay popping

This patch fixes a newly introduced bug where the sender state was
popped before checking that it should be. Amazingly all regressions
pass, but Linux fails to boot on the detailed CPU with caches enabled.
---

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 8f7938b93..2be41642d 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -366,7 +366,7 @@ Cache<TagStore>::recvTimingSnoopResp(PacketPtr pkt)
 
     // must be cache-to-cache response from upper to lower level
     ForwardResponseRecord *rec =
-        dynamic_cast<ForwardResponseRecord *>(pkt->popSenderState());
+        dynamic_cast<ForwardResponseRecord *>(pkt->senderState);
     assert(!system->bypassCaches());
 
     if (rec == NULL) {
@@ -379,6 +379,7 @@ Cache<TagStore>::recvTimingSnoopResp(PacketPtr pkt)
         return;
     }
 
+    pkt->popSenderState();
     pkt->setDest(rec->prevSrc);
     delete rec;
     // @todo someone should pay for this