From: Jiong Wang Date: Fri, 23 Sep 2016 10:54:14 +0000 (+0000) Subject: [PATCH 16/17][ARM] Add tests for VFP FP16 ACLE instrinsics. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=da9b2e696a433e3d201b02d42e21e3e29c8f920a;p=gcc.git [PATCH 16/17][ARM] Add tests for VFP FP16 ACLE instrinsics. testsuite/ 2016-09-23 Jiong Wang Matthew Wahab * gcc.target/aarch64/advsimd-intrinsics/binary_scalar_op.inc: New. * gcc.target/aarch64/advsimd-intrinsics/unary_scalar_op.inc: New. * gcc.target/aarch64/advsimd-intrinsics/ternary_scalar_op.inc: New. * gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c: New. * gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c: New. Co-Authored-By: Matthew Wahab From-SVN: r240426 --- diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2c3577019dc..bc9e798cc8f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,44 @@ +2016-09-23 Jiong Wang + Matthew Wahab + + * gcc.target/aarch64/advsimd-intrinsics/binary_scalar_op.inc: New. + * gcc.target/aarch64/advsimd-intrinsics/unary_scalar_op.inc: New. + * gcc.target/aarch64/advsimd-intrinsics/ternary_scalar_op.inc: New. + * gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c: New. + * gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c: New. + 2016-09-23 Matthew Wahab * gcc.target/arm/armv8_2-fp16-neon-1.c: New. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_scalar_op.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_scalar_op.inc new file mode 100644 index 00000000000..55dedd43262 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_scalar_op.inc @@ -0,0 +1,160 @@ +/* Template file for binary scalar operator validation. + + This file is meant to be included by test files for binary scalar + operations. */ + +/* Check for required settings. */ + +#ifndef INSN_NAME +#error INSN_NAME (the intrinsic to test) must be defined. +#endif + +#ifndef INPUT_TYPE +#error INPUT_TYPE (basic type of an input value) must be defined. +#endif + +#ifndef OUTPUT_TYPE +#error OUTPUT_TYPE (basic type of an output value) must be defined. +#endif + +#ifndef OUTPUT_TYPE_SIZE +#error OUTPUT_TYPE_SIZE (size in bits of an output value) must be defined. +#endif + +/* Optional settings: + + INPUT_1: Input values for the first parameter. Must be of type INPUT_TYPE. + INPUT_2: Input values for the first parameter. Must be of type + INPUT_TYPE. */ + +#ifndef TEST_MSG +#define TEST_MSG "unnamed test" +#endif + +/* The test framework. */ + +#include + +extern void abort (); + +#define INFF __builtin_inf () + +/* Stringify a macro. */ +#define STR0(A) #A +#define STR(A) STR0 (A) + +/* Macro concatenation. */ +#define CAT0(A, B) A##B +#define CAT(A, B) CAT0 (A, B) + +/* Format strings for error reporting. */ +#define FMT16 "0x%04x" +#define FMT32 "0x%08x" +#define FMT CAT (FMT,OUTPUT_TYPE_SIZE) + +/* Type construction: forms TS_t, where T is the base type and S the size in + bits. */ +#define MK_TYPE0(T, S) T##S##_t +#define MK_TYPE(T, S) MK_TYPE0 (T, S) + +/* Convenience types for input and output data. */ +typedef MK_TYPE (uint, OUTPUT_TYPE_SIZE) output_hex_type; + +/* Conversion between typed values and their hexadecimal representation. */ +typedef union +{ + OUTPUT_TYPE value; + output_hex_type hex; +} output_conv_type; + +/* Default input values. */ + +float16_t input_1_float16_t[] = +{ + 0.0, -0.0, + 2.0, 3.1, + 20.0, 0.40, + -2.3, 1.33, + -7.6, 0.31, + 0.3353, 0.5, + 1.0, 13.13, + -6.3, 20.0, + (float16_t)INFF, (float16_t)-INFF, +}; + +float16_t input_2_float16_t[] = +{ + 1.0, 1.0, + -4.33, 100.0, + 30.0, -0.02, + 0.5, -7.231, + -6.3, 20.0, + -7.231, 2.3, + -7.6, 5.1, + 0.31, 0.33353, + (float16_t)-INFF, (float16_t)INFF, +}; + +#ifndef INPUT_1 +#define INPUT_1 CAT (input_1_,INPUT_TYPE) +#endif + +#ifndef INPUT_2 +#define INPUT_2 CAT (input_2_,INPUT_TYPE) +#endif + +/* Support macros and routines for the test function. */ + +#define CHECK() \ + { \ + output_conv_type actual; \ + output_conv_type expect; \ + \ + expect.hex = ((output_hex_type*)EXPECTED)[index]; \ + actual.value = INSN_NAME ((INPUT_1)[index], \ + (INPUT_2)[index]); \ + \ + if (actual.hex != expect.hex) \ + { \ + fprintf (stderr, \ + "ERROR in %s (%s line %d), buffer %s, " \ + "index %d: got " \ + FMT " != " FMT "\n", \ + TEST_MSG, __FILE__, __LINE__, \ + STR (EXPECTED), index, \ + actual.hex, expect.hex); \ + abort (); \ + } \ + fprintf (stderr, "CHECKED %s %s\n", \ + STR (EXPECTED), TEST_MSG); \ + } + +#define FNNAME1(NAME) exec_ ## NAME +#define FNNAME(NAME) FNNAME1 (NAME) + +/* The test function. */ + +void +FNNAME (INSN_NAME) (void) +{ + /* Basic test: y[i] = OP (x[i]), for each INPUT[i], then compare the result + against EXPECTED[i]. */ + + const int num_tests = sizeof (INPUT_1) / sizeof (INPUT_1[0]); + int index; + + for (index = 0; index < num_tests; index++) + CHECK (); + +#ifdef EXTRA_TESTS + EXTRA_TESTS (); +#endif +} + +int +main (void) +{ + FNNAME (INSN_NAME) (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ternary_scalar_op.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ternary_scalar_op.inc new file mode 100644 index 00000000000..47650912d85 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ternary_scalar_op.inc @@ -0,0 +1,206 @@ +/* Template file for ternary scalar operator validation. + + This file is meant to be included by test files for binary scalar + operations. */ + +/* Check for required settings. */ + +#ifndef INSN_NAME +#error INSN_NAME (the intrinsic to test) must be defined. +#endif + +#ifndef INPUT_TYPE +#error INPUT_TYPE (basic type of an input value) must be defined. +#endif + +#ifndef OUTPUT_TYPE +#error OUTPUT_TYPE (basic type of an output value) must be defined. +#endif + +#ifndef OUTPUT_TYPE_SIZE +#error OUTPUT_TYPE_SIZE (size in bits of an output value) must be defined. +#endif + +/* Optional settings: + + INPUT_1: Input values for the first parameter. Must be of type INPUT_TYPE. + INPUT_2: Input values for the second parameter. Must be of type INPUT_TYPE. + INPUT_3: Input values for the third parameter. Must be of type + INPUT_TYPE. */ + +#ifndef TEST_MSG +#define TEST_MSG "unnamed test" +#endif + +/* The test framework. */ + +#include + +extern void abort (); + +#define INFF __builtin_inf () + +/* Stringify a macro. */ +#define STR0(A) #A +#define STR(A) STR0 (A) + +/* Macro concatenation. */ +#define CAT0(A, B) A##B +#define CAT(A, B) CAT0 (A, B) + +/* Format strings for error reporting. */ +#define FMT16 "0x%04x" +#define FMT32 "0x%08x" +#define FMT CAT (FMT,OUTPUT_TYPE_SIZE) + +/* Type construction: forms TS_t, where T is the base type and S the size in + bits. */ +#define MK_TYPE0(T, S) T##S##_t +#define MK_TYPE(T, S) MK_TYPE0 (T, S) + +/* Convenience types for input and output data. */ +typedef MK_TYPE (uint, OUTPUT_TYPE_SIZE) output_hex_type; + +/* Conversion between typed values and their hexadecimal representation. */ +typedef union +{ + OUTPUT_TYPE value; + output_hex_type hex; +} output_conv_type; + +/* Default input values. */ + +float16_t input_1_float16_t[] = +{ + 0.0, + -0.0, + 2.0, + 3.1, + 20.0, + 0.40, + -2.3, + 1.33, + -7.6, + 0.31, + 0.3353, + 0.5, + 1.0, + 13.13, + -6.3, + 20.0, + (float16_t)INFF, + (float16_t)-INFF, +}; + +float16_t input_2_float16_t[] = +{ + 1.0, + 1.0, + -4.33, + 100.0, + 30.0, + -0.02, + 0.5, + -7.231, + -6.3, + 20.0, + -7.231, + 2.3, + -7.6, + 5.1, + 0.31, + 0.33353, + (float16_t)-INFF, + (float16_t)INFF, +}; + +float16_t input_3_float16_t[] = +{ + -0.0, + 0.0, + 0.31, + -0.31, + 1.31, + 2.1, + -6.3, + 1.0, + -1.5, + 5.1, + 0.3353, + 9.3, + -9.3, + -7.231, + 0.5, + -0.33, + (float16_t)INFF, + (float16_t)INFF, +}; + +#ifndef INPUT_1 +#define INPUT_1 CAT (input_1_,INPUT_TYPE) +#endif + +#ifndef INPUT_2 +#define INPUT_2 CAT (input_2_,INPUT_TYPE) +#endif + +#ifndef INPUT_3 +#define INPUT_3 CAT (input_3_,INPUT_TYPE) +#endif + +/* Support macros and routines for the test function. */ + +#define CHECK() \ + { \ + output_conv_type actual; \ + output_conv_type expect; \ + \ + expect.hex = ((output_hex_type*)EXPECTED)[index]; \ + actual.value = INSN_NAME ((INPUT_1)[index], \ + (INPUT_2)[index], \ + (INPUT_3)[index]); \ + \ + if (actual.hex != expect.hex) \ + { \ + fprintf (stderr, \ + "ERROR in %s (%s line %d), buffer %s, " \ + "index %d: got " \ + FMT " != " FMT "\n", \ + TEST_MSG, __FILE__, __LINE__, \ + STR (EXPECTED), index, \ + actual.hex, expect.hex); \ + abort (); \ + } \ + fprintf (stderr, "CHECKED %s %s\n", \ + STR (EXPECTED), TEST_MSG); \ + } + +#define FNNAME1(NAME) exec_ ## NAME +#define FNNAME(NAME) FNNAME1 (NAME) + +/* The test function. */ + +void +FNNAME (INSN_NAME) (void) +{ + /* Basic test: y[i] = OP (x[i]), for each INPUT[i], then compare the result + against EXPECTED[i]. */ + + const int num_tests = sizeof (INPUT_1) / sizeof (INPUT_1[0]); + int index; + + for (index = 0; index < num_tests; index++) + CHECK (); + +#ifdef EXTRA_TESTS + EXTRA_TESTS (); +#endif +} + +int +main (void) +{ + FNNAME (INSN_NAME) (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_scalar_op.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_scalar_op.inc new file mode 100644 index 00000000000..86403d28ae6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_scalar_op.inc @@ -0,0 +1,199 @@ +/* Template file for unary scalar operator validation. + + This file is meant to be included by test files for unary scalar + operations. */ + +/* Check for required settings. */ + +#ifndef INSN_NAME +#error INSN_NAME (the intrinsic to test) must be defined. +#endif + +#ifndef INPUT_TYPE +#error INPUT_TYPE (basic type of an input value) must be defined. +#endif + +#ifndef SCALAR_OPERANDS +#ifndef EXPECTED +#error EXPECTED (an array of expected output values) must be defined. +#endif +#endif + +#ifndef OUTPUT_TYPE +#error OUTPUT_TYPE (basic type of an output value) must be defined. +#endif + +#ifndef OUTPUT_TYPE_SIZE +#error OUTPUT_TYPE_SIZE (size in bits of an output value) must be defined. +#endif + +/* Optional settings. */ + +/* SCALAR_OPERANDS: Defined iff the intrinsic has a scalar operand. + + SCALAR_1, SCALAR_2, .., SCALAR_4: If SCALAR_OPERANDS is defined, SCALAR_ + is the scalar and EXPECTED_ is array of expected values. + + INPUT: Input values for the first parameter. Must be of type INPUT_TYPE. */ + +/* Additional comments for the error message. */ +#ifndef COMMENT +#define COMMENT "" +#endif + +#ifndef TEST_MSG +#define TEST_MSG "unnamed test" +#endif + +/* The test framework. */ + +#include + +extern void abort (); + +#define INFF __builtin_inf () + +/* Stringify a macro. */ +#define STR0(A) #A +#define STR(A) STR0 (A) + +/* Macro concatenation. */ +#define CAT0(A, B) A##B +#define CAT(A, B) CAT0 (A, B) + +/* Format strings for error reporting. */ +#define FMT16 "0x%04x" +#define FMT32 "0x%08x" +#define FMT CAT (FMT,OUTPUT_TYPE_SIZE) + +/* Type construction: forms TS_t, where T is the base type and S the size in + bits. */ +#define MK_TYPE0(T, S) T##S##_t +#define MK_TYPE(T, S) MK_TYPE0 (T, S) + +/* Convenience types for input and output data. */ +typedef MK_TYPE (uint, OUTPUT_TYPE_SIZE) output_hex_type; + +/* Conversion between typed values and their hexadecimal representation. */ +typedef union +{ + OUTPUT_TYPE value; + output_hex_type hex; +} output_conv_type; + +/* Default input values. */ + +float16_t input_1_float16_t[] = +{ + 0.0, -0.0, + 2.0, 3.1, + 20.0, 0.40, + -2.3, 1.33, + -7.6, 0.31, + 0.3353, 0.5, + 1.0, 13.13, + -6.3, 20.0, + (float16_t)INFF, (float16_t)-INFF, +}; + +#ifndef INPUT +#define INPUT CAT(input_1_,INPUT_TYPE) +#endif + +/* Support macros and routines for the test function. */ + +#define CHECK() \ + { \ + output_conv_type actual; \ + output_conv_type expect; \ + \ + expect.hex = ((output_hex_type*)EXPECTED)[index]; \ + actual.value = INSN_NAME ((INPUT)[index]); \ + \ + if (actual.hex != expect.hex) \ + { \ + fprintf (stderr, \ + "ERROR in %s (%s line %d), buffer %s, " \ + "index %d: got " \ + FMT " != " FMT "\n", \ + TEST_MSG, __FILE__, __LINE__, \ + STR (EXPECTED), index, \ + actual.hex, expect.hex); \ + abort (); \ + } \ + fprintf (stderr, "CHECKED %s %s\n", \ + STR (EXPECTED), TEST_MSG); \ + } + +#define CHECK_N(SCALAR, EXPECTED) \ + { \ + output_conv_type actual; \ + output_conv_type expect; \ + \ + expect.hex \ + = ((output_hex_type*)EXPECTED)[index]; \ + actual.value = INSN_NAME ((INPUT)[index], (SCALAR)); \ + \ + if (actual.hex != expect.hex) \ + { \ + fprintf (stderr, \ + "ERROR in %s (%s line %d), buffer %s, " \ + "index %d: got " \ + FMT " != " FMT "\n", \ + TEST_MSG, __FILE__, __LINE__, \ + STR (EXPECTED), index, \ + actual.hex, expect.hex); \ + abort (); \ + } \ + fprintf (stderr, "CHECKED %s %s\n", \ + STR (EXPECTED), TEST_MSG); \ + } + +#define FNNAME1(NAME) exec_ ## NAME +#define FNNAME(NAME) FNNAME1 (NAME) + +/* The test function. */ + +void +FNNAME (INSN_NAME) (void) +{ + /* Basic test: y[i] = OP (x[i]), for each INPUT[i], then compare the result + against EXPECTED[i]. */ + + const int num_tests = sizeof (INPUT) / sizeof (INPUT[0]); + int index; + + for (index = 0; index < num_tests; index++) + { +#if defined (SCALAR_OPERANDS) + +#ifdef SCALAR_1 + CHECK_N (SCALAR_1, EXPECTED_1); +#endif +#ifdef SCALAR_2 + CHECK_N (SCALAR_2, EXPECTED_2); +#endif +#ifdef SCALAR_3 + CHECK_N (SCALAR_3, EXPECTED_3); +#endif +#ifdef SCALAR_4 + CHECK_N (SCALAR_4, EXPECTED_4); +#endif + +#else /* !defined (SCALAR_OPERAND). */ + CHECK (); +#endif + } + +#ifdef EXTRA_TESTS + EXTRA_TESTS (); +#endif +} + +int +main (void) +{ + FNNAME (INSN_NAME) (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c new file mode 100644 index 00000000000..16a986ac590 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Expected results (16-bit hexadecimal representation). */ +uint16_t expected[] = +{ + 0x0000 /* 0.000000 */, + 0x0000 /* 0.000000 */, + 0x4000 /* 2.000000 */, + 0x4233 /* 3.099609 */, + 0x4d00 /* 20.000000 */, + 0x3666 /* 0.399902 */, + 0x409a /* 2.300781 */, + 0x3d52 /* 1.330078 */, + 0x479a /* 7.601562 */, + 0x34f6 /* 0.310059 */, + 0x355d /* 0.335205 */, + 0x3800 /* 0.500000 */, + 0x3c00 /* 1.000000 */, + 0x4a91 /* 13.132812 */, + 0x464d /* 6.300781 */, + 0x4d00 /* 20.000000 */, + 0x7c00 /* inf */, + 0x7c00 /* inf */ +}; + +#define TEST_MSG "VABSH_F16" +#define INSN_NAME vabsh_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c new file mode 100644 index 00000000000..4b0e24284f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Expected results (16-bit hexadecimal representation). */ +uint16_t expected[] = +{ + 0x3c00 /* 1.000000 */, + 0x3c00 /* 1.000000 */, + 0xc0a8 /* -2.328125 */, + 0x5672 /* 103.125000 */, + 0x5240 /* 50.000000 */, + 0x3614 /* 0.379883 */, + 0xbf34 /* -1.800781 */, + 0xc5e6 /* -5.898438 */, + 0xcaf4 /* -13.906250 */, + 0x4d14 /* 20.312500 */, + 0xc6e5 /* -6.894531 */, + 0x419a /* 2.800781 */, + 0xc69a /* -6.601562 */, + 0x4c8f /* 18.234375 */, + 0xc5fe /* -5.992188 */, + 0x4d15 /* 20.328125 */, + 0x7e00 /* nan */, + 0x7e00 /* nan */, +}; + +#define TEST_MSG "VADDH_F16" +#define INSN_NAME vaddh_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "binary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c new file mode 100644 index 00000000000..ebfd62a1068 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Input values. */ +float16_t input[] = +{ + 0.0, -0.0, + 123.4, -567.8, + -34.8, 1024, + 663.1, 169.1, + -4.8, 77.0, + -144.5, -56.8, + + (float16_t) -16, (float16_t) -15, + (float16_t) -14, (float16_t) -13, +}; + +/* Expected results (32-bit hexadecimal representation). */ +uint32_t expected[] = +{ + 0x00000000, + 0x00000000, + 0x0000007b, + 0xfffffdc8, + 0xffffffdd, + 0x00000400, + 0x00000297, + 0x000000a9, + 0xfffffffb, + 0x0000004d, + 0xffffff6f, + 0xffffffc7, + 0xfffffff0, + 0xfffffff1, + 0xfffffff2, + 0xfffffff3 +}; + +#define TEST_MSG "VCVTAH_S32_F16" +#define INSN_NAME vcvtah_s32_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE int32_t +#define OUTPUT_TYPE_SIZE 32 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c new file mode 100644 index 00000000000..5ae28fc11db --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Input values. */ +float16_t input[] = +{ + 0.0, -0.0, + 123.4, -567.8, + -34.8, 1024, + 663.1, 169.1, + -4.8, 77.0, + -144.5, -56.8, + + (float16_t) -16, (float16_t) -15, + (float16_t) -14, (float16_t) -13, +}; + +/* Expected results (32-bit hexadecimal representation). */ +uint32_t expected[] = +{ + 0x00000000, + 0x00000000, + 0x0000007b, + 0x00000000, + 0x00000000, + 0x00000400, + 0x00000297, + 0x000000a9, + 0x00000000, + 0x0000004d, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000 +}; + +#define TEST_MSG "VCVTAH_U32_F16" +#define INSN_NAME vcvtah_u32_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint32_t +#define OUTPUT_TYPE_SIZE 32 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c new file mode 100644 index 00000000000..2173a0ef4ee --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Input values. */ +uint32_t input[] = +{ + 0, -0, + 123, -567, + -34, 1024, + -63, 169, + -4, 77, + -144, -56, + -16, -15, + -14, -13, +}; + +/* Expected results (16-bit hexadecimal representation). */ +uint16_t expected[] = +{ + 0x0000 /* 0.000000 */, + 0x0000 /* 0.000000 */, + 0x57b0 /* 123.000000 */, + 0xe06e /* -567.000000 */, + 0xd040 /* -34.000000 */, + 0x6400 /* 1024.000000 */, + 0xd3e0 /* -63.000000 */, + 0x5948 /* 169.000000 */, + 0xc400 /* -4.000000 */, + 0x54d0 /* 77.000000 */, + 0xd880 /* -144.000000 */, + 0xd300 /* -56.000000 */, + 0xcc00 /* -16.000000 */, + 0xcb80 /* -15.000000 */, + 0xcb00 /* -14.000000 */, + 0xca80 /* -13.000000 */ +}; + +#define TEST_MSG "VCVTH_F16_S32" +#define INSN_NAME vcvth_f16_s32 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE uint32_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c new file mode 100644 index 00000000000..15832023a05 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Input values. */ +int32_t input[] = +{ + 0, -0, + 123, -567, + -34, 1024, + -63, 169, + -4, 77, + -144, -56, + -16, -15, + -14, -13, +}; + +/* Expected results (16-bit hexadecimal representation). */ +uint16_t expected[] = +{ + 0x0000 /* 0.000000 */, + 0x0000 /* 0.000000 */, + 0x57b0 /* 123.000000 */, + 0x7c00 /* inf */, + 0x7c00 /* inf */, + 0x6400 /* 1024.000000 */, + 0x7c00 /* inf */, + 0x5948 /* 169.000000 */, + 0x7c00 /* inf */, + 0x54d0 /* 77.000000 */, + 0x7c00 /* inf */, + 0x7c00 /* inf */, + 0x7c00 /* inf */, + 0x7c00 /* inf */, + 0x7c00 /* inf */, + 0x7c00 /* inf */ +}; + +#define TEST_MSG "VCVTH_F16_U32" +#define INSN_NAME vcvth_f16_u32 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE int32_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c new file mode 100644 index 00000000000..9ce95581f69 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c @@ -0,0 +1,99 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Input values. */ +uint32_t input[] = +{ + 0, -0, + 123, -567, + -34, 1024, + -63, 169, + -4, 77, + -144, -56, + -16, -15, + -14, -13, +}; + +/* Expected results (16-bit hexadecimal representation). */ +uint16_t expected_1[] = +{ + 0x0000 /* 0.000000 */, + 0x0000 /* 0.000000 */, + 0x53b0 /* 61.500000 */, + 0xdc6e /* -283.500000 */, + 0xcc40 /* -17.000000 */, + 0x6000 /* 512.000000 */, + 0xcfe0 /* -31.500000 */, + 0x5548 /* 84.500000 */, + 0xc000 /* -2.000000 */, + 0x50d0 /* 38.500000 */, + 0xd480 /* -72.000000 */, + 0xcf00 /* -28.000000 */, + 0xc800 /* -8.000000 */, + 0xc780 /* -7.500000 */, + 0xc700 /* -7.000000 */, + 0xc680 /* -6.500000 */ +}; + +uint16_t expected_2[] = +{ + 0x0000 /* 0.000000 */, + 0x0000 /* 0.000000 */, + 0x4fb0 /* 30.750000 */, + 0xd86e /* -141.750000 */, + 0xc840 /* -8.500000 */, + 0x5c00 /* 256.000000 */, + 0xcbe0 /* -15.750000 */, + 0x5148 /* 42.250000 */, + 0xbc00 /* -1.000000 */, + 0x4cd0 /* 19.250000 */, + 0xd080 /* -36.000000 */, + 0xcb00 /* -14.000000 */, + 0xc400 /* -4.000000 */, + 0xc380 /* -3.750000 */, + 0xc300 /* -3.500000 */, + 0xc280 /* -3.250000 */ +}; + +uint16_t expected_3[] = +{ + 0x0000 /* 0.000000 */, + 0x0000 /* 0.000000 */, + 0x0000 /* 0.000000 */, + 0x8002 /* -0.000000 */, + 0x8000 /* -0.000000 */, + 0x0004 /* 0.000000 */, + 0x8000 /* -0.000000 */, + 0x0001 /* 0.000000 */, + 0x8000 /* -0.000000 */, + 0x0000 /* 0.000000 */, + 0x8001 /* -0.000000 */, + 0x8000 /* -0.000000 */, + 0x8000 /* -0.000000 */, + 0x8000 /* -0.000000 */, + 0x8000 /* -0.000000 */, + 0x8000 /* -0.000000 */ +}; + +#define TEST_MSG "VCVTH_N_F16_S32" +#define INSN_NAME vcvth_n_f16_s32 + +#define INPUT input +#define EXPECTED_1 expected_1 +#define EXPECTED_2 expected_2 +#define EXPECTED_3 expected_3 + +#define INPUT_TYPE int32_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +#define SCALAR_OPERANDS +#define SCALAR_1 1 +#define SCALAR_2 2 +#define SCALAR_3 32 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c new file mode 100644 index 00000000000..d308c35bea1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c @@ -0,0 +1,99 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Input values. */ +uint32_t input[] = +{ + 0, -0, + 123, -567, + -34, 1024, + -63, 169, + -4, 77, + -144, -56, + -16, -15, + -14, -13, +}; + +/* Expected results (16-bit hexadecimal representation). */ +uint16_t expected_1[] = +{ + 0x0000 /* 0.000000 */, + 0x0000 /* 0.000000 */, + 0x53b0 /* 61.500000 */, + 0x7c00 /* inf */, + 0x7c00 /* inf */, + 0x6000 /* 512.000000 */, + 0x7c00 /* inf */, + 0x5548 /* 84.500000 */, + 0x7c00 /* inf */, + 0x50d0 /* 38.500000 */, + 0x7c00 /* inf */, + 0x7c00 /* inf */, + 0x7c00 /* inf */, + 0x7c00 /* inf */, + 0x7c00 /* inf */, + 0x7c00 /* inf */ +}; + +uint16_t expected_2[] = +{ + 0x0000 /* 0.000000 */, + 0x0000 /* 0.000000 */, + 0x4fb0 /* 30.750000 */, + 0x7c00 /* inf */, + 0x7c00 /* inf */, + 0x5c00 /* 256.000000 */, + 0x7c00 /* inf */, + 0x5148 /* 42.250000 */, + 0x7c00 /* inf */, + 0x4cd0 /* 19.250000 */, + 0x7c00 /* inf */, + 0x7c00 /* inf */, + 0x7c00 /* inf */, + 0x7c00 /* inf */, + 0x7c00 /* inf */, + 0x7c00 /* inf */ +}; + +uint16_t expected_3[] = +{ + 0x0000 /* 0.000000 */, + 0x0000 /* 0.000000 */, + 0x0000 /* 0.000000 */, + 0x3c00 /* 1.000000 */, + 0x3c00 /* 1.000000 */, + 0x0004 /* 0.000000 */, + 0x3c00 /* 1.000000 */, + 0x0001 /* 0.000000 */, + 0x3c00 /* 1.000000 */, + 0x0000 /* 0.000000 */, + 0x3c00 /* 1.000000 */, + 0x3c00 /* 1.000000 */, + 0x3c00 /* 1.000000 */, + 0x3c00 /* 1.000000 */, + 0x3c00 /* 1.000000 */, + 0x3c00 /* 1.000000 */ +}; + +#define TEST_MSG "VCVTH_N_F16_U32" +#define INSN_NAME vcvth_n_f16_u32 + +#define INPUT input +#define EXPECTED_1 expected_1 +#define EXPECTED_2 expected_2 +#define EXPECTED_3 expected_3 + +#define INPUT_TYPE uint32_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +#define SCALAR_OPERANDS +#define SCALAR_1 1 +#define SCALAR_2 2 +#define SCALAR_3 32 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c new file mode 100644 index 00000000000..6e2ee500cf8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c @@ -0,0 +1,100 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Input values. */ +float16_t input[] = +{ + 0.0, -0.0, + 123.4, -567.8, + -34.8, 1024, + 663.1, 169.1, + -4.8, 77.0, + -144.5, -56.8, + + (float16_t) -16, (float16_t) -15, + (float16_t) -14, (float16_t) -13, +}; + +/* Expected results (32-bit hexadecimal representation). */ +uint32_t expected_1[] = +{ + 0x00000000, + 0x00000000, + 0x000000f6, + 0xfffffb90, + 0xffffffbb, + 0x00000800, + 0x0000052e, + 0x00000152, + 0xfffffff7, + 0x0000009a, + 0xfffffedf, + 0xffffff8f, + 0xffffffe0, + 0xffffffe2, + 0xffffffe4, + 0xffffffe6, +}; + +uint32_t expected_2[] = +{ + 0x00000000, + 0x00000000, + 0x000001ed, + 0xfffff720, + 0xffffff75, + 0x00001000, + 0x00000a5c, + 0x000002a4, + 0xffffffed, + 0x00000134, + 0xfffffdbe, + 0xffffff1d, + 0xffffffc0, + 0xffffffc4, + 0xffffffc8, + 0xffffffcc, +}; + +uint32_t expected_3[] = +{ + 0x00000000, + 0x00000000, + 0x7fffffff, + 0x80000000, + 0x80000000, + 0x7fffffff, + 0x7fffffff, + 0x7fffffff, + 0x80000000, + 0x7fffffff, + 0x80000000, + 0x80000000, + 0x80000000, + 0x80000000, + 0x80000000, + 0x80000000, +}; + +#define TEST_MSG "VCVTH_N_S32_F16" +#define INSN_NAME vcvth_n_s32_f16 + +#define INPUT input +#define EXPECTED_1 expected_1 +#define EXPECTED_2 expected_2 +#define EXPECTED_3 expected_3 + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint32_t +#define OUTPUT_TYPE_SIZE 32 + +#define SCALAR_OPERANDS +#define SCALAR_1 1 +#define SCALAR_2 2 +#define SCALAR_3 32 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c new file mode 100644 index 00000000000..188f60cafe1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c @@ -0,0 +1,100 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Input values. */ +float16_t input[] = +{ + 0.0, -0.0, + 123.4, -567.8, + -34.8, 1024, + 663.1, 169.1, + -4.8, 77.0, + -144.5, -56.8, + + (float16_t) -16, (float16_t) -15, + (float16_t) -14, (float16_t) -13, +}; + +/* Expected results (32-bit hexadecimal representation). */ +uint32_t expected_1[] = +{ + 0x00000000, + 0x00000000, + 0x000000f6, + 0x00000000, + 0x00000000, + 0x00000800, + 0x0000052e, + 0x00000152, + 0x00000000, + 0x0000009a, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +uint32_t expected_2[] = +{ + 0x00000000, + 0x00000000, + 0x000001ed, + 0x00000000, + 0x00000000, + 0x00001000, + 0x00000a5c, + 0x000002a4, + 0x00000000, + 0x00000134, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +uint32_t expected_3[] = +{ + 0x00000000, + 0x00000000, + 0xffffffff, + 0x00000000, + 0x00000000, + 0xffffffff, + 0xffffffff, + 0xffffffff, + 0x00000000, + 0xffffffff, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +#define TEST_MSG "VCVTH_N_U32_F16" +#define INSN_NAME vcvth_n_u32_f16 + +#define INPUT input +#define EXPECTED_1 expected_1 +#define EXPECTED_2 expected_2 +#define EXPECTED_3 expected_3 + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint32_t +#define OUTPUT_TYPE_SIZE 32 + +#define SCALAR_OPERANDS +#define SCALAR_1 1 +#define SCALAR_2 2 +#define SCALAR_3 32 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c new file mode 100644 index 00000000000..6bff9546531 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Input values. */ +float16_t input[] = +{ + 0.0, -0.0, + 123.4, -567.8, + -34.8, 1024, + 663.1, 169.1, + -4.8, 77.0, + -144.5, -56.8, + + (float16_t) -16, (float16_t) -15, + (float16_t) -14, (float16_t) -13, +}; + +/* Expected results (32-bit hexadecimal representation). */ +uint32_t expected[] = +{ + 0x00000000, + 0x00000000, + 0x0000007b, + 0xfffffdc8, + 0xffffffde, + 0x00000400, + 0x00000297, + 0x000000a9, + 0xfffffffc, + 0x0000004d, + 0xffffff70, + 0xffffffc8, + 0xfffffff0, + 0xfffffff1, + 0xfffffff2, + 0xfffffff3, +}; + +#define TEST_MSG "VCVTH_S32_F16" +#define INSN_NAME vcvth_s32_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE int32_t +#define OUTPUT_TYPE_SIZE 32 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c new file mode 100644 index 00000000000..d5807d74317 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Input values. */ +float16_t input[] = +{ + 0.0, -0.0, + 123.4, -567.8, + -34.8, 1024, + 663.1, 169.1, + -4.8, 77.0, + -144.5, -56.8, + + (float16_t) -16, (float16_t) -15, + (float16_t) -14, (float16_t) -13, +}; + +/* Expected results (32-bit hexadecimal representation). */ +uint32_t expected[] = +{ + 0x00000000, + 0x00000000, + 0x0000007b, + 0x00000000, + 0x00000000, + 0x00000400, + 0x00000297, + 0x000000a9, + 0x00000000, + 0x0000004d, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +#define TEST_MSG "VCVTH_U32_F16" +#define INSN_NAME vcvth_u32_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint32_t +#define OUTPUT_TYPE_SIZE 32 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c new file mode 100644 index 00000000000..f4f7b374d3e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Input values. */ +float16_t input[] = +{ + 0.0, -0.0, + 123.4, -567.8, + -34.8, 1024, + 663.1, 169.1, + -4.8, 77.0, + -144.5, -56.8, + + (float16_t) -16, (float16_t) -15, + (float16_t) -14, (float16_t) -13, +}; + +/* Expected results (32-bit hexadecimal representation). */ +uint32_t expected[] = +{ + 0x00000000, + 0x00000000, + 0x0000007b, + 0xfffffdc8, + 0xffffffdd, + 0x00000400, + 0x00000297, + 0x000000a9, + 0xfffffffb, + 0x0000004d, + 0xffffff6f, + 0xffffffc7, + 0xfffffff0, + 0xfffffff1, + 0xfffffff2, + 0xfffffff3 +}; + +#define TEST_MSG "VCVTMH_S32_F16" +#define INSN_NAME vcvtmh_s32_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE int32_t +#define OUTPUT_TYPE_SIZE 32 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c new file mode 100644 index 00000000000..6cda3b63601 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Input values. */ +float16_t input[] = +{ + 0.0, -0.0, + 123.4, -567.8, + -34.8, 1024, + 663.1, 169.1, + -4.8, 77.0, + -144.5, -56.8, + + (float16_t) -16, (float16_t) -15, + (float16_t) -14, (float16_t) -13, +}; + +/* Expected results (32-bit hexadecimal representation). */ +uint32_t expected[] = +{ + 0x00000000, + 0x00000000, + 0x0000007b, + 0x00000000, + 0x00000000, + 0x00000400, + 0x00000297, + 0x000000a9, + 0x00000000, + 0x0000004d, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +#define TEST_MSG "VCVTMH_U32_F16" +#define INSN_NAME vcvtmh_u32_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint32_t +#define OUTPUT_TYPE_SIZE 32 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c new file mode 100644 index 00000000000..94c333ee44c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Input values. */ +float16_t input[] = +{ + 0.0, -0.0, + 123.4, -567.8, + -34.8, 1024, + 663.1, 169.1, + -4.8, 77.0, + -144.5, -56.8, + + (float16_t) -16, (float16_t) -15, + (float16_t) -14, (float16_t) -13, +}; + +/* Expected results (32-bit hexadecimal representation). */ +uint32_t expected[] = +{ + 0x00000000, + 0x00000000, + 0x0000007b, + 0xfffffdc8, + 0xffffffdd, + 0x00000400, + 0x00000297, + 0x000000a9, + 0xfffffffb, + 0x0000004d, + 0xffffff70, + 0xffffffc7, + 0xfffffff0, + 0xfffffff1, + 0xfffffff2, + 0xfffffff3 +}; + +#define TEST_MSG "VCVTNH_S32_F16" +#define INSN_NAME vcvtnh_s32_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE int32_t +#define OUTPUT_TYPE_SIZE 32 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c new file mode 100644 index 00000000000..97d5fbabb3f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Input values. */ +float16_t input[] = +{ + 0.0, -0.0, + 123.4, -567.8, + -34.8, 1024, + 663.1, 169.1, + -4.8, 77.0, + -144.5, -56.8, + + (float16_t) -16, (float16_t) -15, + (float16_t) -14, (float16_t) -13, +}; + +/* Expected results (32-bit hexadecimal representation). */ +uint32_t expected[] = +{ + 0x00000000, + 0x00000000, + 0x0000007b, + 0x00000000, + 0x00000000, + 0x00000400, + 0x00000297, + 0x000000a9, + 0x00000000, + 0x0000004d, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +#define TEST_MSG "VCVTNH_U32_F16" +#define INSN_NAME vcvtnh_u32_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint32_t +#define OUTPUT_TYPE_SIZE 32 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c new file mode 100644 index 00000000000..105d2367175 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Input values. */ +float16_t input[] = +{ + 0.0, -0.0, + 123.4, -567.8, + -34.8, 1024, + 663.1, 169.1, + -4.8, 77.0, + -144.5, -56.8, + + (float16_t) -16, (float16_t) -15, + (float16_t) -14, (float16_t) -13, +}; + +/* Expected results (32-bit hexadecimal representation). */ +uint32_t expected[] = +{ + 0x00000000, + 0x00000000, + 0x0000007c, + 0xfffffdc8, + 0xffffffde, + 0x00000400, + 0x00000297, + 0x000000aa, + 0xfffffffc, + 0x0000004d, + 0xffffff70, + 0xffffffc8, + 0xfffffff0, + 0xfffffff1, + 0xfffffff2, + 0xfffffff3 +}; + +#define TEST_MSG "VCVTPH_S32_F16" +#define INSN_NAME vcvtph_s32_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE int32_t +#define OUTPUT_TYPE_SIZE 32 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c new file mode 100644 index 00000000000..d66adcd44a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Input values. */ +float16_t input[] = +{ + 0.0, -0.0, + 123.4, -567.8, + -34.8, 1024, + 663.1, 169.1, + -4.8, 77.0, + -144.5, -56.8, + + (float16_t) -16, (float16_t) -15, + (float16_t) -14, (float16_t) -13, +}; + +/* Expected results (32-bit hexadecimal representation). */ +uint32_t expected[] = +{ + 0x00000000, + 0x00000000, + 0x0000007c, + 0x00000000, + 0x00000000, + 0x00000400, + 0x00000297, + 0x000000aa, + 0x00000000, + 0x0000004d, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +#define TEST_MSG "VCVTPH_U32_F16" +#define INSN_NAME vcvtph_u32_f16 + +#define INPUT input +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE uint32_t +#define OUTPUT_TYPE_SIZE 32 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c new file mode 100644 index 00000000000..6a991098efd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +#define INFF __builtin_inf () + +/* Expected results (16-bit hexadecimal representation). */ +uint16_t expected[] = +{ + 0x0000 /* 0.000000 */, + 0x8000 /* -0.000000 */, + 0xb765 /* -0.462158 */, + 0x27ef /* 0.030991 */, + 0x3955 /* 0.666504 */, + 0xccff /* -19.984375 */, + 0xc49a /* -4.601562 */, + 0xb1e3 /* -0.183960 */, + 0x3cd3 /* 1.206055 */, + 0x23f0 /* 0.015503 */, + 0xa9ef /* -0.046356 */, + 0x32f4 /* 0.217285 */, + 0xb036 /* -0.131592 */, + 0x4126 /* 2.574219 */, + 0xcd15 /* -20.328125 */, + 0x537f /* 59.968750 */, + 0x7e00 /* nan */, + 0x7e00 /* nan */ +}; + +#define TEST_MSG "VDIVH_F16" +#define INSN_NAME vdivh_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "binary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c new file mode 100644 index 00000000000..1ac6b67ba8b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Expected results (16-bit hexadecimal representation). */ +uint16_t expected[] = +{ + 0x0000 /* 0.000000 */, + 0x0000 /* 0.000000 */, + 0x3944 /* 0.658203 */, + 0xcefa /* -27.906250 */, + 0x5369 /* 59.281250 */, + 0x35ba /* 0.357910 */, + 0xc574 /* -5.453125 */, + 0xc5e6 /* -5.898438 */, + 0x3f66 /* 1.849609 */, + 0x5665 /* 102.312500 */, + 0xc02d /* -2.087891 */, + 0x4d79 /* 21.890625 */, + 0x547b /* 71.687500 */, + 0xcdf0 /* -23.750000 */, + 0xc625 /* -6.144531 */, + 0x4cf9 /* 19.890625 */, + 0x7e00 /* nan */, + 0x7e00 /* nan */ +}; + +#define TEST_MSG "VFMAH_F16" +#define INSN_NAME vfmah_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "ternary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c new file mode 100644 index 00000000000..77021bec615 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Expected results (16-bit hexadecimal representation). */ +uint16_t expected[] = +{ + 0x0000 /* 0.000000 */, + 0x8000 /* -0.000000 */, + 0x42af /* 3.341797 */, + 0x5043 /* 34.093750 */, + 0xccd2 /* -19.281250 */, + 0x3712 /* 0.441895 */, + 0x3acc /* 0.849609 */, + 0x4848 /* 8.562500 */, + 0xcc43 /* -17.046875 */, + 0xd65c /* -101.750000 */, + 0x4185 /* 2.759766 */, + 0xcd39 /* -20.890625 */, + 0xd45b /* -69.687500 */, + 0x5241 /* 50.031250 */, + 0xc675 /* -6.457031 */, + 0x4d07 /* 20.109375 */, + 0x7c00 /* inf */, + 0xfc00 /* -inf */ +}; + +#define TEST_MSG "VFMSH_F16" +#define INSN_NAME vfmsh_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "ternary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c new file mode 100644 index 00000000000..4db4b84885e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +#define INFF __builtin_inf () + +/* Expected results (16-bit hexadecimal representation). */ +uint16_t expected[] = +{ + 0x3c00 /* 1.000000 */, + 0x3c00 /* 1.000000 */, + 0x4000 /* 2.000000 */, + 0x5640 /* 100.000000 */, + 0x4f80 /* 30.000000 */, + 0x3666 /* 0.399902 */, + 0x3800 /* 0.500000 */, + 0x3d52 /* 1.330078 */, + 0xc64d /* -6.300781 */, + 0x4d00 /* 20.000000 */, + 0x355d /* 0.335205 */, + 0x409a /* 2.300781 */, + 0x3c00 /* 1.000000 */, + 0x4a91 /* 13.132812 */, + 0x34f6 /* 0.310059 */, + 0x4d00 /* 20.000000 */, + 0x7c00 /* inf */, + 0x7c00 /* inf */ +}; + +#define TEST_MSG "VMAXNMH_F16" +#define INSN_NAME vmaxnmh_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "binary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c new file mode 100644 index 00000000000..f6b02161fa4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +#define INFF __builtin_inf () + +/* Expected results (16-bit hexadecimal representation). */ +uint16_t expected[] = +{ + 0x0000 /* 0.000000 */, + 0x8000 /* -0.000000 */, + 0xc454 /* -4.328125 */, + 0x4233 /* 3.099609 */, + 0x4d00 /* 20.000000 */, + 0xa51f /* -0.020004 */, + 0xc09a /* -2.300781 */, + 0xc73b /* -7.230469 */, + 0xc79a /* -7.601562 */, + 0x34f6 /* 0.310059 */, + 0xc73b /* -7.230469 */, + 0x3800 /* 0.500000 */, + 0xc79a /* -7.601562 */, + 0x451a /* 5.101562 */, + 0xc64d /* -6.300781 */, + 0x3556 /* 0.333496 */, + 0xfc00 /* -inf */, + 0xfc00 /* -inf */ +}; + +#define TEST_MSG "VMINNMH_F16" +#define INSN_NAME vminnmh_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "binary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c new file mode 100644 index 00000000000..09684d24d3c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +#define INFF __builtin_inf () + +/* Expected results (16-bit hexadecimal representation). */ +uint16_t expected[] = +{ + 0x0000 /* 0.000000 */, + 0x8000 /* -0.000000 */, + 0xc854 /* -8.656250 */, + 0x5cd8 /* 310.000000 */, + 0x60b0 /* 600.000000 */, + 0xa019 /* -0.008003 */, + 0xbc9a /* -1.150391 */, + 0xc8cf /* -9.617188 */, + 0x51fd /* 47.906250 */, + 0x4634 /* 6.203125 */, + 0xc0d9 /* -2.423828 */, + 0x3c9a /* 1.150391 */, + 0xc79a /* -7.601562 */, + 0x5430 /* 67.000000 */, + 0xbfd0 /* -1.953125 */, + 0x46ac /* 6.671875 */, + 0xfc00 /* -inf */, + 0xfc00 /* -inf */ +}; + +#define TEST_MSG "VMULH_F16" +#define INSN_NAME vmulh_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "binary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c new file mode 100644 index 00000000000..421d8277fd3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c @@ -0,0 +1,39 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +uint16_t expected[] = +{ + 0x8000 /* -0.000000 */, + 0x0000 /* 0.000000 */, + 0xc000 /* -2.000000 */, + 0xc233 /* -3.099609 */, + 0xcd00 /* -20.000000 */, + 0xb666 /* -0.399902 */, + 0x409a /* 2.300781 */, + 0xbd52 /* -1.330078 */, + 0x479a /* 7.601562 */, + 0xb4f6 /* -0.310059 */, + 0xb55d /* -0.335205 */, + 0xb800 /* -0.500000 */, + 0xbc00 /* -1.000000 */, + 0xca91 /* -13.132812 */, + 0x464d /* 6.300781 */, + 0xcd00 /* -20.000000 */, + 0xfc00 /* -inf */, + 0x7c00 /* inf */ +}; + +#define TEST_MSG "VNEGH_F16" +#define INSN_NAME vnegh_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c new file mode 100644 index 00000000000..bcf47f658d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Expected results (16-bit hexadecimal representation). */ +uint16_t expected[] = +{ + 0x0000 /* 0.000000 */, + 0x8000 /* -0.000000 */, + 0x4000 /* 2.000000 */, + 0x4200 /* 3.000000 */, + 0x4d00 /* 20.000000 */, + 0x0000 /* 0.000000 */, + 0xc000 /* -2.000000 */, + 0x3c00 /* 1.000000 */, + 0xc800 /* -8.000000 */, + 0x0000 /* 0.000000 */, + 0x0000 /* 0.000000 */, + 0x3c00 /* 1.000000 */, + 0x3c00 /* 1.000000 */, + 0x4a80 /* 13.000000 */, + 0xc600 /* -6.000000 */, + 0x4d00 /* 20.000000 */, + 0x7c00 /* inf */, + 0xfc00 /* -inf */ +}; + +#define TEST_MSG "VRNDAH_F16" +#define INSN_NAME vrndah_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c new file mode 100644 index 00000000000..3c4649eb19f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Expected results (16-bit hexadecimal representation). */ +uint16_t expected[] = +{ + 0x0000 /* 0.000000 */, + 0x8000 /* -0.000000 */, + 0x4000 /* 2.000000 */, + 0x4200 /* 3.000000 */, + 0x4d00 /* 20.000000 */, + 0x0000 /* 0.000000 */, + 0xc000 /* -2.000000 */, + 0x3c00 /* 1.000000 */, + 0xc700 /* -7.000000 */, + 0x0000 /* 0.000000 */, + 0x0000 /* 0.000000 */, + 0x0000 /* 0.000000 */, + 0x3c00 /* 1.000000 */, + 0x4a80 /* 13.000000 */, + 0xc600 /* -6.000000 */, + 0x4d00 /* 20.000000 */, + 0x7c00 /* inf */, + 0xfc00 /* -inf */ +}; + +#define TEST_MSG "VRNDH_F16" +#define INSN_NAME vrndh_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c new file mode 100644 index 00000000000..4a7b721a511 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Expected results (16-bit hexadecimal representation). */ +uint16_t expected[] = +{ + 0x0000 /* 0.000000 */, + 0x8000 /* -0.000000 */, + 0x4000 /* 2.000000 */, + 0x4200 /* 3.000000 */, + 0x4d00 /* 20.000000 */, + 0x0000 /* 0.000000 */, + 0xc000 /* -2.000000 */, + 0x3c00 /* 1.000000 */, + 0xc800 /* -8.000000 */, + 0x0000 /* 0.000000 */, + 0x0000 /* 0.000000 */, + 0x0000 /* 0.000000 */, + 0x3c00 /* 1.000000 */, + 0x4a80 /* 13.000000 */, + 0xc600 /* -6.000000 */, + 0x4d00 /* 20.000000 */, + 0x7c00 /* inf */, + 0xfc00 /* -inf */ +}; + +#define TEST_MSG "VRNDIH_F16" +#define INSN_NAME vrndih_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c new file mode 100644 index 00000000000..9af357dbd4a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Expected results (16-bit hexadecimal representation). */ +uint16_t expected[] = +{ + 0x0000 /* 0.000000 */, + 0x8000 /* -0.000000 */, + 0x4000 /* 2.000000 */, + 0x4200 /* 3.000000 */, + 0x4d00 /* 20.000000 */, + 0x0000 /* 0.000000 */, + 0xc200 /* -3.000000 */, + 0x3c00 /* 1.000000 */, + 0xc800 /* -8.000000 */, + 0x0000 /* 0.000000 */, + 0x0000 /* 0.000000 */, + 0x0000 /* 0.000000 */, + 0x3c00 /* 1.000000 */, + 0x4a80 /* 13.000000 */, + 0xc700 /* -7.000000 */, + 0x4d00 /* 20.000000 */, + 0x7c00 /* inf */, + 0xfc00 /* -inf */ +}; + +#define TEST_MSG "VRNDMH_F16" +#define INSN_NAME vrndmh_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c new file mode 100644 index 00000000000..eb4b27dda94 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Expected results (16-bit hexadecimal representation). */ +uint16_t expected[] = +{ + 0x0000 /* 0.000000 */, + 0x8000 /* -0.000000 */, + 0x4000 /* 2.000000 */, + 0x4200 /* 3.000000 */, + 0x4d00 /* 20.000000 */, + 0x0000 /* 0.000000 */, + 0xc000 /* -2.000000 */, + 0x3c00 /* 1.000000 */, + 0xc800 /* -8.000000 */, + 0x0000 /* 0.000000 */, + 0x0000 /* 0.000000 */, + 0x0000 /* 0.000000 */, + 0x3c00 /* 1.000000 */, + 0x4a80 /* 13.000000 */, + 0xc600 /* -6.000000 */, + 0x4d00 /* 20.000000 */, + 0x7c00 /* inf */, + 0xfc00 /* -inf */ +}; + +#define TEST_MSG "VRNDNH_F16" +#define INSN_NAME vrndnh_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c new file mode 100644 index 00000000000..3fa9749cbf3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Expected results (16-bit hexadecimal representation). */ +uint16_t expected[] = +{ + 0x0000 /* 0.000000 */, + 0x8000 /* -0.000000 */, + 0x4000 /* 2.000000 */, + 0x4400 /* 4.000000 */, + 0x4d00 /* 20.000000 */, + 0x3c00 /* 1.000000 */, + 0xc000 /* -2.000000 */, + 0x4000 /* 2.000000 */, + 0xc700 /* -7.000000 */, + 0x3c00 /* 1.000000 */, + 0x3c00 /* 1.000000 */, + 0x3c00 /* 1.000000 */, + 0x3c00 /* 1.000000 */, + 0x4b00 /* 14.000000 */, + 0xc600 /* -6.000000 */, + 0x4d00 /* 20.000000 */, + 0x7c00 /* inf */, + 0xfc00 /* -inf */ +}; + +#define TEST_MSG "VRNDPH_F16" +#define INSN_NAME vrndph_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c new file mode 100644 index 00000000000..eb4b27dda94 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Expected results (16-bit hexadecimal representation). */ +uint16_t expected[] = +{ + 0x0000 /* 0.000000 */, + 0x8000 /* -0.000000 */, + 0x4000 /* 2.000000 */, + 0x4200 /* 3.000000 */, + 0x4d00 /* 20.000000 */, + 0x0000 /* 0.000000 */, + 0xc000 /* -2.000000 */, + 0x3c00 /* 1.000000 */, + 0xc800 /* -8.000000 */, + 0x0000 /* 0.000000 */, + 0x0000 /* 0.000000 */, + 0x0000 /* 0.000000 */, + 0x3c00 /* 1.000000 */, + 0x4a80 /* 13.000000 */, + 0xc600 /* -6.000000 */, + 0x4d00 /* 20.000000 */, + 0x7c00 /* inf */, + 0xfc00 /* -inf */ +}; + +#define TEST_MSG "VRNDNH_F16" +#define INSN_NAME vrndnh_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c new file mode 100644 index 00000000000..7d038277782 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +/* Expected results (16-bit hexadecimal representation). */ +uint16_t expected[] = +{ + 0x0000 /* 0.000000 */, + 0x8000 /* -0.000000 */, + 0x3da8 /* 1.414062 */, + 0x3f0b /* 1.760742 */, + 0x4479 /* 4.472656 */, + 0x390f /* 0.632324 */, + 0x7e00 /* nan */, + 0x3c9d /* 1.153320 */, + 0x7e00 /* nan */, + 0x3874 /* 0.556641 */, + 0x38a2 /* 0.579102 */, + 0x39a8 /* 0.707031 */, + 0x3c00 /* 1.000000 */, + 0x433f /* 3.623047 */, + 0x7e00 /* nan */, + 0x4479 /* 4.472656 */, + 0x7c00 /* inf */, + 0x7e00 /* nan */ +}; + +#define TEST_MSG "VSQRTH_F16" +#define INSN_NAME vsqrth_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for unary scalar operations. */ +#include "unary_scalar_op.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c new file mode 100644 index 00000000000..a7aba11aaff --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include + +#define INFF __builtin_inf () + +/* Expected results (16-bit hexadecimal representation). */ +uint16_t expected[] = +{ + 0xbc00 /* -1.000000 */, + 0xbc00 /* -1.000000 */, + 0x4654 /* 6.328125 */, + 0xd60e /* -96.875000 */, + 0xc900 /* -10.000000 */, + 0x36b8 /* 0.419922 */, + 0xc19a /* -2.800781 */, + 0x4848 /* 8.562500 */, + 0xbd34 /* -1.300781 */, + 0xccec /* -19.687500 */, + 0x4791 /* 7.566406 */, + 0xbf34 /* -1.800781 */, + 0x484d /* 8.601562 */, + 0x4804 /* 8.031250 */, + 0xc69c /* -6.609375 */, + 0x4ceb /* 19.671875 */, + 0x7c00 /* inf */, + 0xfc00 /* -inf */ +}; + +#define TEST_MSG "VSUB_F16" +#define INSN_NAME vsubh_f16 + +#define EXPECTED expected + +#define INPUT_TYPE float16_t +#define OUTPUT_TYPE float16_t +#define OUTPUT_TYPE_SIZE 16 + +/* Include the template for binary scalar operations. */ +#include "binary_scalar_op.inc"