From: Tiago Mück <tiago.muck@arm.com>
Date: Tue, 15 Oct 2019 21:01:13 +0000 (-0500)
Subject: mem-ruby: removed checkCoherence from MOESI_CMP_directory
X-Git-Tag: v20.1.0.0~661
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=daa3dc556eb665d997e9869b5230357542e2c9cf;p=gem5.git

mem-ruby: removed checkCoherence from MOESI_CMP_directory

The implementation is empty and this is not used by other protocols

Change-Id: Iaed7d6d4b7ef1eb4cd47bdc0710dc9dbb7a86a0c
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21923
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
index b8d8ab4a0..d7b175c7e 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
@@ -215,7 +215,6 @@ machine(MachineType:L1Cache, "L1 cache protocol")
          ((cache_entry.CacheState != State:O) && (state == State:O)) ) {
 
         cache_entry.CacheState := state;
-        sequencer.checkCoherence(addr);
       }
       else {
         cache_entry.CacheState := state;
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
index 5dfc6a9dd..0faa03ff2 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
@@ -522,13 +522,6 @@ machine(MachineType:L2Cache, "Token protocol")
                 (state == State:SLS)) {
        assert(is_valid(cache_entry));
        assert(L2cache.isTagPresent(addr));
-
-       if ( ((cache_entry.CacheState != State:M) && (state == State:M)) ||
-           ((cache_entry.CacheState != State:S) && (state == State:S)) ||
-           ((cache_entry.CacheState != State:O) && (state == State:O)) ) {
-        // disable Coherence Checker for now
-        // sequencer.checkCoherence(addr);
-      }
     } else if ( (state == State:ILS) ||
                 (state == State:ILX) ||
                 (state == State:ILO) ||
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
index 6f868b49d..70035e2d9 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
@@ -156,9 +156,6 @@ machine(MachineType:Directory, "Directory protocol")
     assert(getDirectoryEntry(addr).Sharers.count() == 0);
 
     directory.deallocate(addr);
-
-    // disable coherence checker
-    // sequencer.checkCoherence(addr);
   }
 
   State getState(TBE tbe, Addr addr) {