From: Luke Kenneth Casson Leighton Date: Sun, 25 Nov 2018 06:21:00 +0000 (+0000) Subject: minor reorg, add alu X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=daafe882cb591c8e3a3a04f74561cc941cde52f7;p=rv32.git minor reorg, add alu --- diff --git a/cpu.py b/cpu.py index 07ba973..4e769f9 100644 --- a/cpu.py +++ b/cpu.py @@ -47,8 +47,19 @@ class MemoryInterface: rw_wait = Signal(name="memory_interface_rw_wait") +class Decoder: + funct7 = Signal(7, name="decoder_funct7") + funct3 = Signal(3, name="decoder_funct3") + rd = Signal(5, name="decoder_rd") + rs1 = Signal(5, name="decoder_rs1") + rs2 = Signal(5, name="decoder_rs2") + immediate = Signal(32, name="decoder_immediate") + opcode = Signal(7, name="decoder_opcode") + act = Signal(decode_action, name="decoder_action") + + class CPU(Module): - """ + """ """ def get_ls_misaligned(self, ls, funct3, load_store_address_low_2): @@ -59,16 +70,16 @@ class CPU(Module): "default": ls.eq(Constant(1)) }) - def get_lsbm(self, decoder_funct3): + def get_lsbm(self, dc): return Cat(Constant(1), - Mux((decoder_funct3[1] | decoder_funct3[0]), + Mux((dc.funct3[1] | dc.funct3[0]), Constant(1), Constant(0)), - Mux((decoder_funct3[1]), + Mux((dc.funct3[1]), Constant(0b11, 2), Constant(0, 2))) def __init__(self): - #self.clk = ClockSignal() - #self.reset = ResetSignal() + self.clk = ClockSignal() + self.reset = ResetSignal() self.tty_write = Signal() self.tty_write_data = Signal(8) self.tty_write_busy = Signal() @@ -140,49 +151,42 @@ class CPU(Module): ) self.specials += fs - decoder_funct7 = Signal(7) - decoder_funct3 = Signal(3) - decoder_rd = Signal(5) - decoder_rs1 = Signal(5) - decoder_rs2 = Signal(5) - decoder_immediate = Signal(32) - decoder_opcode = Signal(7) - decode_act = Signal(decode_action) + dc = Decoder() cd = Instance("CPUDecoder", name="decoder", i_instruction = fetch_output_instruction, - o_funct7 = decoder_funct7, - o_funct3 = decoder_funct3, - o_rd = decoder_rd, - o_rs1 = decoder_rs1, - o_rs2 = decoder_rs2, - o_immediate = decoder_immediate, - o_opcode = decoder_opcode, - o_decode_action = decode_act + o_funct7 = dc.funct7, + o_funct3 = dc.funct3, + o_rd = dc.rd, + o_rs1 = dc.rs1, + o_rs2 = dc.rs2, + o_immediate = dc.immediate, + o_opcode = dc.opcode, + o_decode_action = dc.act ) self.specials += cd register_rs1 = Signal(32) register_rs2 = Signal(32) - self.comb += If(decoder_rs1 == 0, + self.comb += If(dc.rs1 == 0, register_rs1.eq(0) ).Else( - register_rs1.eq(registers[decoder_rs1-1])) - self.comb += If(decoder_rs2 == 0, + register_rs1.eq(registers[dc.rs1-1])) + self.comb += If(dc.rs2 == 0, register_rs2.eq(0) ).Else( - register_rs2.eq(registers[decoder_rs2-1])) + register_rs2.eq(registers[dc.rs2-1])) load_store_address = Signal(32) load_store_address_low_2 = Signal(2) - self.comb += load_store_address.eq(decoder_immediate + register_rs1) + self.comb += load_store_address.eq(dc.immediate + register_rs1) self.comb += load_store_address_low_2.eq( - decoder_immediate[:2] + register_rs1[:2]) + dc.immediate[:2] + register_rs1[:2]) load_store_misaligned = Signal() - lsa = self.get_ls_misaligned(load_store_misaligned, decoder_funct3, + lsa = self.get_ls_misaligned(load_store_misaligned, dc.funct3, load_store_address_low_2) self.comb += lsa @@ -191,8 +195,7 @@ class CPU(Module): unshifted_load_store_byte_mask = Signal(4) - self.comb += unshifted_load_store_byte_mask.eq(self.get_lsbm( - decoder_funct3)) + self.comb += unshifted_load_store_byte_mask.eq(self.get_lsbm(dc)) # XXX yuck. this will cause migen simulation to fail # (however conversion to verilog works) @@ -232,18 +235,35 @@ class CPU(Module): loaded_value = Signal(32) b0 = unmasked_loaded_value[0:8] - b1 = Mux(decoder_funct3[0:2] == 0, - Replicate(~decoder_funct3[2] & unmasked_loaded_value[7], 8), + b1 = Mux(dc.funct3[0:2] == 0, + Replicate(~dc.funct3[2] & unmasked_loaded_value[7], 8), unmasked_loaded_value[8:16]) - b2 = Mux(decoder_funct3[1] == 0, - Replicate(~decoder_funct3[2] & - Mux(decoder_funct3[0], unmasked_loaded_value[15], + b2 = Mux(dc.funct3[1] == 0, + Replicate(~dc.funct3[2] & + Mux(dc.funct3[0], unmasked_loaded_value[15], unmasked_loaded_value[7]), 16), unmasked_loaded_value[16:32]) self.comb += loaded_value.eq(Cat(b0, b1, b2)) + self.comb += mi.rw_active.eq(~self.reset + & (fetch_output_st == fetch_output_state_valid) + & ~load_store_misaligned + & ((dc.act & (DA.load | DA.store)) != 0)) + + self.comb += mi.rw_read_not_write.eq(~dc.opcode[5]) + + # alu + alu_a = Signal(32) + alu_b = Signal(32) + alu_result = Signal(32) + + self.comb += alu_a.eq(register_rs1) + self.comb += alu_b.eq(Mux(dc.opcode[5], + register_rs2, + dc.immediate)) + if __name__ == "__main__": example = CPU() print(verilog.convert(example, @@ -259,17 +279,6 @@ if __name__ == "__main__": """ - assign memory_interface_rw_active = ~reset - & (fetch_output_state == `fetch_output_state_valid) - & ~load_store_misaligned - & ((decode_action & (`decode_action_load | `decode_action_store)) != 0); - - assign memory_interface_rw_read_not_write = ~decoder_opcode[5]; - - wire [31:0] alu_a = register_rs1; - wire [31:0] alu_b = decoder_opcode[5] ? register_rs2 : decoder_immediate; - wire [31:0] alu_result; - cpu_alu alu( .funct7(decoder_funct7), .funct3(decoder_funct3), @@ -691,7 +700,7 @@ if __name__ == "__main__": endcase end endfunction - + assign csr_op_is_valid = get_csr_op_is_valid(csr_number, csr_reads, csr_writes); wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter