From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Mon, 26 Aug 2013 18:33:34 +0000 (+0200)
Subject: bus/wb2lasmi: use existing interface to determine WB width to be consistent with... 
X-Git-Tag: 24jan2021_ls180~2099^2~468
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dac10f5570615a70a670347b08ad9919e8738f5d;p=litex.git

bus/wb2lasmi: use existing interface to determine WB width to be consistent with other modules
---

diff --git a/migen/bus/wishbone2lasmi.py b/migen/bus/wishbone2lasmi.py
index d8ce1d5b..39a9daeb 100644
--- a/migen/bus/wishbone2lasmi.py
+++ b/migen/bus/wishbone2lasmi.py
@@ -6,11 +6,14 @@ from migen.genlib.record import Record, layout_len
 
 # cachesize (in 32-bit words) is the size of the data store, must be a power of 2
 class WB2LASMI(Module):
-	def __init__(self, cachesize, lasmim, data_width=32):
-		self.wishbone = wishbone.Interface()
+	def __init__(self, cachesize, lasmim, wbm=None):
+		if wbm is None:
+			wbm = wishbone.Interface()
+		self.wishbone = wbm
 
 		###
 
+		data_width = flen(self.wishbone.dat_r)
 		if lasmim.dw < data_width:
 			raise ValueError("LASMI data width must be >= {dw}".format(dw=data_width))
 		if (lasmim.dw % data_width) != 0: