From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 14 Oct 2018 16:33:24 +0000 (+0100)
Subject: add category descriptions
X-Git-Tag: convert-csv-opcode-to-binary~4936
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dac71983e1118fc7f524a7006884a43498c4cdbb;p=libreriscv.git

add category descriptions
---

diff --git a/simple_v_extension/opcodes.mdwn b/simple_v_extension/opcodes.mdwn
index 1bcf29253..efe05fbcf 100644
--- a/simple_v_extension/opcodes.mdwn
+++ b/simple_v_extension/opcodes.mdwn
@@ -6,6 +6,9 @@ page categorises and identifies the type of parallelism that SimpleV
 indirectly adds on each RISC-V **standard** opcode.  These are note-form:
 see [[specification]] for full details.
 
+Note that the list is necessarily incomplete, as any custom or future
+extensions may also benefit from fitting one of the categories below.
+
 * **-** no change of behaviour takes place: operation remains
   **completely scalar** as an **unmodified**, unaugmented standard RISC-V
   opcode, even if it has registers.