From: lkcl <lkcl@web>
Date: Sun, 15 May 2022 16:25:06 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2224
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dacea9604cf7a26c5b0c07eb6db7f1687e34a19b;p=libreriscv.git

---

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index a6b421f71..7223f89a2 100644
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -275,10 +275,10 @@ uint_xlen_t intabsacc(uint_xlen_t rs, int_xlen_t ra, int_xlen_t rb) {
 }
 ```
 
-For SVP64 these use EXTRA2 and allow Twin Elwidths. The reason is so
-that the Register used as an Accumulator (RS) may have its own
-Element Width Override. This allows e.g. a 16 bit accumulator for 8 bit
-differences.
+For SVP64, the twin Elwidths allows e.g. a 16 bit accumulator for 8 bit
+differences.  Form is `RM-1P-3S1D` where RS-as-source has a separate
+SVP64 designation from RS-as-dest. This gives a limited range of
+non-overwrite capability.
 
 # shift-and-add