From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Sun, 11 Dec 2011 19:16:50 +0000 (+0100)
Subject: bus: 14-bit CSR addresses
X-Git-Tag: 24jan2021_ls180~2099^2~1146
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dad91206531d7e3ad48cf5c6ff9ce978a622f19c;p=litex.git

bus: 14-bit CSR addresses
---

diff --git a/migen/bus/csr.py b/migen/bus/csr.py
index 297bd4e4..667d58b8 100644
--- a/migen/bus/csr.py
+++ b/migen/bus/csr.py
@@ -2,7 +2,7 @@ from migen.fhdl import structure as f
 from .simple import Simple
 
 _desc = [
-	(True,	"a",	16),
+	(True,	"a",	14),
 	(True,	"we",	1),
 	(True,	"d",	32),
 	(False,	"d",	32)
diff --git a/migen/bus/wishbone2csr.py b/migen/bus/wishbone2csr.py
index 6d009904..9c0a4c24 100644
--- a/migen/bus/wishbone2csr.py
+++ b/migen/bus/wishbone2csr.py
@@ -14,7 +14,7 @@ class Inst():
 		sync = [
 			f.Assign(self.csr.we_o, self.wishbone.we_i),
 			f.Assign(self.csr.d_o, self.wishbone.dat_i),
-			f.Assign(self.csr.a_o, self.wishbone.adr_i[:16]),
+			f.Assign(self.csr.a_o, self.wishbone.adr_i[2:16]),
 			f.Assign(self.wishbone.ack_o, 0),
 			f.Assign(self.wishbone.dat_o, self.csr.d_i)
 		]