From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 7 Apr 2020 18:27:15 +0000 (+0100)
Subject: note that CR must be offset by 32
X-Git-Tag: div_pipeline~1435^2~39
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=daec7884b0063698ee2125f6dfe4744b3ddcbf5e;p=soc.git

note that CR must be offset by 32
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 8a4da033..deb30fc7 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -148,7 +148,7 @@ class ISACaller:
         # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
 
         # create CR then allow portions of it to be "selectable" (below)
-        self.cr = SelectableInt(0, 32)
+        self.cr = SelectableInt(0, 32) # TODO, must be bits range 32-63 not 0-31
 
         # "undefined", just set to variable-bit-width int (use exts "max")
         self.undefined = SelectableInt(0, 256) # TODO, not hard-code 256!