From: Eric Anholt <eric@anholt.net>
Date: Wed, 10 Jun 2020 19:59:38 +0000 (-0700)
Subject: freedreno/a6xx: Define the register fields for polygon fill mode.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=daee177ca0285bac842b3485dfbb3d8591401261;p=mesa.git

freedreno/a6xx: Define the register fields for polygon fill mode.

Produced by comparing the traces of:
dEQP-VK.rasterization.culling.front_triangles
dEQP-VK.rasterization.culling.front_triangles_point
dEQP-VK.rasterization.culling.front_triangles_line

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5650>
---

diff --git a/src/freedreno/registers/a6xx.xml b/src/freedreno/registers/a6xx.xml
index 32c280370b5..32a5c077855 100644
--- a/src/freedreno/registers/a6xx.xml
+++ b/src/freedreno/registers/a6xx.xml
@@ -159,6 +159,12 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 </enum>
 
 <!-- probably same as a5xx -->
+<enum name="a6xx_polygon_mode">
+	<value name="POLYMODE6_POINTS" value="1"/>
+	<value name="POLYMODE6_LINES" value="2"/>
+	<value name="POLYMODE6_TRIANGLES" value="3"/>
+</enum>
+
 <enum name="a6xx_depth_format">
 	<value name="DEPTH6_NONE" value="0"/>
 	<value name="DEPTH6_16" value="1"/>
@@ -2530,7 +2536,9 @@ to upconvert to 32b float internally?
 
 	<reg32 offset="0x9106" name="VPC_UNKNOWN_9106"/>
 	<reg32 offset="0x9107" name="VPC_UNKNOWN_9107"/>
-	<reg32 offset="0x9108" name="VPC_UNKNOWN_9108"/>
+	<reg32 offset="0x9108" name="VPC_POLYGON_MODE">
+		<bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
+	</reg32>
 
 	<array offset="0x9200" name="VPC_VARYING_INTERP" stride="1" length="8">
 		<reg32 offset="0x0" name="MODE"/>
@@ -2690,7 +2698,10 @@ to upconvert to 32b float internally?
 	</reg32>
 
 	<reg32 offset="0x9980" name="PC_UNKNOWN_9980"/>
-	<reg32 offset="0x9981" name="PC_UNKNOWN_9981"/>
+
+	<reg32 offset="0x9981" name="PC_POLYGON_MODE">
+		<bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
+	</reg32>
 
 	<reg32 offset="0x9990" name="PC_UNKNOWN_9990"/>
 
diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c
index e59cabb9756..7371f9489ca 100644
--- a/src/freedreno/vulkan/tu_cmd_buffer.c
+++ b/src/freedreno/vulkan/tu_cmd_buffer.c
@@ -968,9 +968,9 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
-   tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9981, 0x3);
+   tu_cs_emit_write_reg(cs, REG_A6XX_PC_POLYGON_MODE, POLYMODE6_TRIANGLES);
    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
-   tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
+   tu_cs_emit_write_reg(cs, REG_A6XX_VPC_POLYGON_MODE, POLYMODE6_TRIANGLES);
    tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
 
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
index a55bb053e04..78000296625 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
@@ -1194,9 +1194,9 @@ fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
 	WRITE(REG_A6XX_VPC_UNKNOWN_9210, 0);
 	WRITE(REG_A6XX_VPC_UNKNOWN_9211, 0);
 	WRITE(REG_A6XX_VPC_UNKNOWN_9602, 0);
-	WRITE(REG_A6XX_PC_UNKNOWN_9981, 0x3);
+	WRITE(REG_A6XX_PC_POLYGON_MODE, POLYMODE6_TRIANGLES);
 	WRITE(REG_A6XX_PC_UNKNOWN_9E72, 0);
-	WRITE(REG_A6XX_VPC_UNKNOWN_9108, 0x3);
+	WRITE(REG_A6XX_VPC_POLYGON_MODE, POLYMODE6_TRIANGLES);
 	WRITE(REG_A6XX_SP_TP_SAMPLE_CONFIG, 0);
 	/* NOTE blob seems to (mostly?) use 0xb2 for SP_TP_UNKNOWN_B309
 	 * but this seems to kill texture gather offsets.