From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Mon, 15 Oct 2012 18:32:07 +0000 (+0200)
Subject: transform/unroll_sync: autodetect in/out
X-Git-Tag: 24jan2021_ls180~2099^2~821
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=daee4fb58c94db71885bfacbded5e4b77f8f6a93;p=litex.git

transform/unroll_sync: autodetect in/out
---

diff --git a/examples/basic/multi_accumulator.py b/examples/basic/multi_accumulator.py
index 51352cd3..7f3cf800 100644
--- a/examples/basic/multi_accumulator.py
+++ b/examples/basic/multi_accumulator.py
@@ -19,5 +19,5 @@ ys = [Signal(BV(4)) for i in range(n)]
 accs = [Signal(BV(4)) for i in range(n)]
 zs = [Signal() for i in range(n)]
 
-sync_u = unroll_sync(sync, {x: xs, y: ys}, {acc: accs, z: zs})
+sync_u = unroll_sync(sync, {x: xs, y: ys, acc: accs, z: zs})
 print(verilog.convert(Fragment(sync=sync_u), ios=set(xs+ys+zs)))
diff --git a/migen/transform/unroll.py b/migen/transform/unroll.py
index 644fe7ee..d3a39199 100644
--- a/migen/transform/unroll.py
+++ b/migen/transform/unroll.py
@@ -2,10 +2,11 @@ from itertools import repeat
 
 from migen.fhdl.structure import *
 from migen.fhdl.structure import _Operator, _Slice, _Assign, _ArrayProxy
+from migen.fhdl.tools import list_targets
 
 # y <= y + a + b
 #
-# unroll_sync(sync, {b: [b1, b2], c: [c1, c2]}, {y: [y1, y2]})
+# unroll_sync(sync, {b: [b1, b2], c: [c1, c2], y: [y1, y2]})
 #
 # ==>
 #
@@ -72,6 +73,17 @@ def _list_step_dicts(d):
 		pass
 	return r
 
+def _classify_repl(statements, replacements):
+	targets = list_targets(statements)
+	inputs = {}
+	outputs = {}
+	for k, v in replacements.items():
+		if k in targets:
+			outputs[k] = v
+		else:
+			inputs[k] = v
+	return inputs, outputs
+
 def _variable_for(s, n):
 	sn = s.backtrace[-1][0]
 	if isinstance(sn, str):
@@ -80,7 +92,12 @@ def _variable_for(s, n):
 		name = "v"
 	return Signal(s.bv, name=name, variable=True)
 
-def unroll_sync(statements, inputs, outputs):
+def unroll_sync(statements, replacements):
+	if isinstance(statements, list):
+		sl = statements
+	else:
+		sl = statements(0)
+	inputs, outputs = _classify_repl(sl, replacements)
 	assert(inputs or outputs)
 	if inputs:
 		sd_in = _list_step_dicts(inputs)
@@ -106,10 +123,11 @@ def unroll_sync(statements, inputs, outputs):
 		
 		# replace signals with intermediate variables and copy statements
 		io_var_dict.update(di)
-		if isinstance(statements, list):
-			sl = statements
-		else:
-			sl = statements(n)
+		if n: # done for n = 0 at the beginning of function
+			if isinstance(statements, list):
+				sl = statements
+			else:
+				sl = statements(n)
 		r += _replace(sl, io_var_dict, do_var)
 		
 		# assign to output signals