From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 22 Apr 2020 23:35:35 +0000 (-0700)
Subject: test: ice40_dsp test to read +/ice40/cells_sim.v for default params
X-Git-Tag: working-ls180~594^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=db09e96dff63b7b0fdb7010ad1965aaf261cbe2f;p=yosys.git

test: ice40_dsp test to read +/ice40/cells_sim.v for default params
---

diff --git a/tests/arch/ice40/ice40_dsp.ys b/tests/arch/ice40/ice40_dsp.ys
index 250273859..b13e525fd 100644
--- a/tests/arch/ice40/ice40_dsp.ys
+++ b/tests/arch/ice40/ice40_dsp.ys
@@ -8,4 +8,5 @@ assign o4 = a * b;
 SB_MAC16 m3 (.A(a), .B(b), .O(o5));
 endmodule
 EOT
+read_verilog -lib +/ice40/cells_sim.v
 ice40_dsp