From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 2 May 2020 21:22:37 +0000 (-0700)
Subject: test: add test for #2014
X-Git-Tag: working-ls180~575^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=db13852ed657294d9919e668201abe85bc3fba44;p=yosys.git

test: add test for #2014
---

diff --git a/tests/various/bug2014.ys b/tests/various/bug2014.ys
new file mode 100644
index 000000000..10131fc43
--- /dev/null
+++ b/tests/various/bug2014.ys
@@ -0,0 +1,12 @@
+read_verilog <<EOT
+module test (
+        input signed [1:0] n,
+        output [3:0] dout
+);
+        assign dout = n + 4'sd 4;
+endmodule
+EOT
+
+alumacc
+select -assert-count 1 t:$alu
+equiv_opt -assert opt -fine