From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 27 Jun 2021 12:22:04 +0000 (+0100)
Subject: add SVP64 FFT mode to PowerDecoder, add CSV entries
X-Git-Tag: xlen-bcd~369
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=db1cb550776803538f6434a34ba87df08f155d31;p=openpower-isa.git

add SVP64 FFT mode to PowerDecoder, add CSV entries
---

diff --git a/openpower/isatables/minor_59.csv b/openpower/isatables/minor_59.csv
index 47b948c1..19c143e8 100644
--- a/openpower/isatables/minor_59.csv
+++ b/openpower/isatables/minor_59.csv
@@ -8,7 +8,11 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 -----11000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fres,A,
 -----11001,FPU,OP_FPOP,FRA,NONE,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fmuls,A,
 -----11010,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,frsqrtes,A,
------11100,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fmsubs,A,
------11101,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fmadds,A,
------11110,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fnmsubs,A,
------11111,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fnmadds,A,
+-----11100,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fmsubs,A,~SVP64FFT
+-----11101,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fmadds,A,~SVP64FFT
+-----11110,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fnmsubs,A,~SVP64FFT
+-----11111,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fnmadds,A,~SVP64FFT
+-----11100,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fmsubso,A,SVP64FFT
+-----11101,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fmaddso,A,SVP64FFT
+-----11110,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fnmsubso,A,SVP64FFT
+-----11111,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fnmaddso,A,SVP64FFT
diff --git a/src/openpower/decoder/power_decoder.py b/src/openpower/decoder/power_decoder.py
index e3b2e932..5f9f577c 100644
--- a/src/openpower/decoder/power_decoder.py
+++ b/src/openpower/decoder/power_decoder.py
@@ -324,6 +324,7 @@ class PowerDecoder(Elaboratable):
         if conditions is None:
             # XXX conditions = {}
             conditions = {'SVP64BREV': Const(0, 1),
+                          'SVP64FFT': Const(0, 1),
                          }
         self.actually_does_something = False
         self.pname = name
@@ -768,9 +769,10 @@ if __name__ == '__main__':
 
         def rowsubsetfn(opcode, row):
             log("row_subset", opcode, row)
-            return row['unit'] == 'LDST'
+            return row['unit'] in ['LDST', 'FPU']
 
         conditions = {'SVP64BREV': Signal(name="svp64brev", reset_less=True),
+                      'SVP64FFT': Signal(name="svp64fft", reset_less=True),
                      }
         pdecode = create_pdecode(name="rowsub",
                                  col_subset={'opcode', 'function_unit',
diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index f4a955d5..ecb30ff9 100644
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -755,6 +755,7 @@ class PowerDecodeSubset(Elaboratable):
         if svp64_en:
             self.is_svp64_mode = Signal() # mark decoding as SVP64 Mode
             self.use_svp64_ldst_dec = Signal() # must use LDST decoder
+            self.use_svp64_fft = Signal()      # FFT Mode
             self.sv_rm = SVP64Rec(name="dec_svp64") # SVP64 RM field
             self.rm_dec = SVP64RMModeDecode("svp64_rm_dec")
             # set these to the predicate mask bits needed for the ALU
@@ -779,10 +780,10 @@ class PowerDecodeSubset(Elaboratable):
         # amongst other things
         if svp64_en:
             conditions = {'SVP64BREV': self.use_svp64_ldst_dec,
+                          'SVP64FFT': self.use_svp64_fft,
                          }
         else:
-            conditions = {'SVP64BREV': Const(0, 1),
-                         }
+            conditions = None
 
         # only needed for "main" PowerDecode2
         if not self.final:
@@ -837,6 +838,7 @@ class PowerDecodeSubset(Elaboratable):
             ports += self.sv_rm.ports()
             ports.append(self.is_svp64_mode)
             ports.append(self.use_svp64_ldst_dec )
+            ports.append(self.use_svp64_fft )
         return ports
 
     def needs_field(self, field, op_field):
@@ -953,7 +955,12 @@ class PowerDecodeSubset(Elaboratable):
 
         # rc and oe out
         comb += self.do_copy("rc", dec_rc.rc_out)
-        comb += self.do_copy("oe", dec_oe.oe_out)
+        if self.svp64_en:
+            # OE only enabled when SVP64 not active
+            with m.If(~self.is_svp64_mode):
+                comb += self.do_copy("oe", dec_oe.oe_out)
+        else:
+            comb += self.do_copy("oe", dec_oe.oe_out)
 
         # CR in/out - note: these MUST match with what happens in
         # DecodeCROut!
@@ -997,10 +1004,13 @@ class PowerDecodeSubset(Elaboratable):
             if self.needs_field("imm_data", "in2_sel"):
                 bzero = dec_bi.imm_out.ok & ~dec_bi.imm_out.data.bool()
                 comb += rm_dec.ldst_imz_in.eq(bzero) # B immediate is zero
-            # main PowerDecoder2 determines if bit-reverse mode requested
+            # main PowerDecoder2 determines if different SVP64 modes enabled
             if not self.final:
+                # if bit-reverse mode requested
                 bitrev = rm_dec.ldstmode == SVP64LDSTmode.BITREVERSE
                 comb += self.use_svp64_ldst_dec.eq(bitrev)
+                # if SVP64 FFT mode enabled (overload OE ha ha)
+                comb += self.use_svp64_fft.eq(self.dec.OE)
 
         # decoded/selected instruction flags
         comb += self.do_copy("data_len", self.op_get("ldst_len"))