From: Dave Airlie Date: Tue, 26 Dec 2017 22:02:30 +0000 (+1000) Subject: radv/radeonsi: set dcc min uncompressed properly for APUs. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=db27907d78c05f7266d73a26f052e55e9ddde34c;p=mesa.git radv/radeonsi: set dcc min uncompressed properly for APUs. This is ported from amdvlk. Reviewed-by: Bas Nieuwenhuizen Signed-off-by: Dave Airlie --- diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 5c8d51dedc7..24219d6fa3f 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -3162,6 +3162,15 @@ radv_initialise_color_surface(struct radv_device *device, if (device->physical_device->rad_info.chip_class >= VI) { unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B; + unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B; + + /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and + 64 for APU because all of our APUs to date use DIMMs which have + a request granularity size of 64B while all other chips have a + 32B request size */ + if (!device->physical_device->rad_info.has_dedicated_vram) + min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B; + if (iview->image->info.samples > 1) { if (iview->image->surface.bpe == 1) max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B; @@ -3170,6 +3179,7 @@ radv_initialise_color_surface(struct radv_device *device, } cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) | + S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) | S_028C78_INDEPENDENT_64B_BLOCKS(1); } diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index d2d5dd70ecf..f88bf29e202 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -2451,6 +2451,14 @@ static void si_initialize_color_surface(struct si_context *sctx, if (sctx->b.chip_class >= VI) { unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B; + unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B; + + /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and + 64 for APU because all of our APUs to date use DIMMs which have + a request granularity size of 64B while all other chips have a + 32B request size */ + if (!sctx->screen->info.has_dedicated_vram) + min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B; if (rtex->resource.b.b.nr_samples > 1) { if (rtex->surface.bpe == 1) @@ -2460,6 +2468,7 @@ static void si_initialize_color_surface(struct si_context *sctx, } surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) | + S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) | S_028C78_INDEPENDENT_64B_BLOCKS(1); }