From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 16 Oct 2023 03:54:12 +0000 (-0700)
Subject: put DIVMOD REGEX under new LogType: LogType.OutputMatching
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=db2ef7c822354f0bd07a167c1d41ff1cbec88498;p=openpower-isa.git

put DIVMOD REGEX under new LogType: LogType.OutputMatching
---

diff --git a/src/openpower/test/bigint/powmod.py b/src/openpower/test/bigint/powmod.py
index fd406f78..fab2daa2 100644
--- a/src/openpower/test/bigint/powmod.py
+++ b/src/openpower/test/bigint/powmod.py
@@ -18,7 +18,7 @@ from openpower.test.common import TestAccumulatorBase, skip_case
 from openpower.test.state import ExpectedState
 from openpower.test.util import assemble
 from nmutil.sim_util import hash_256
-from openpower.util import log
+from openpower.util import log, LogType
 from nmutil.plain_data import plain_data
 from cached_property import cached_property
 from openpower.decoder.isa.svshape import SVSHAPE
@@ -252,7 +252,7 @@ class _DivModRegsRegexLogger:
                     value, name, i = value
                     segments.append(f" +{value:08x}")
             segments.append("\\n")
-        log("DIVMOD REGEX:", "".join(segments))
+        log("DIVMOD REGEX:", "".join(segments), kind=LogType.OutputMatching)
 
 
 def python_divmod_shift_sub_algorithm(n, d, width=256, log_regex=False):
diff --git a/src/openpower/util.py b/src/openpower/util.py
index ffc90380..f63a49f0 100644
--- a/src/openpower/util.py
+++ b/src/openpower/util.py
@@ -97,6 +97,7 @@ class LogType(Enum):
     Default = "default"
     InstrInOuts = "instr_in_outs"
     SkipCase = "skip_case"
+    OutputMatching = "output_matching"
 
 
 @lru_cache(typed=True)