From: Mike Frysinger Date: Wed, 22 Sep 2010 21:31:18 +0000 (+0000) Subject: gas: blackfin: reject multiple store insns in parallel insns X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=db3b8e53b58b987469b51761dfda6e198045cd4c;p=binutils-gdb.git gas: blackfin: reject multiple store insns in parallel insns Check for & reject attempts to use multiple store insns in a single parallel insn combination. These are illegal per the Blackfin ISA. Signed-off-by: Robin Getz Signed-off-by: Mike Frysinger --- diff --git a/gas/ChangeLog b/gas/ChangeLog index 102f3075109..b936db5f245 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2010-09-22 Robin Getz + + * config/bfin-parse.y (is_store): New function. + (gen_multi_instr_1): Check parallel slots for store insns. + 2010-09-22 Robin Getz * config/bfin-defs.h (IS_EMUDAT): New define. diff --git a/gas/config/bfin-parse.y b/gas/config/bfin-parse.y index 0dd729cb35b..90d3b0450ed 100644 --- a/gas/config/bfin-parse.y +++ b/gas/config/bfin-parse.y @@ -380,6 +380,36 @@ is_group2 (INSTR_T x) return 0; } +static int +is_store (INSTR_T x) +{ + if (!x) + return 0; + + if ((x->value & 0xf000) == 0x8000) + { + int aop = ((x->value >> 9) & 0x3); + int w = ((x->value >> 11) & 0x1); + if (!w || aop == 3) + return 0; + return 1; + } + + if (((x->value & 0xFF60) == 0x9E60) || /* dagMODim_0 */ + ((x->value & 0xFFF0) == 0x9F60)) /* dagMODik_0 */ + return 0; + + /* decode_dspLDST_0 */ + if ((x->value & 0xFC00) == 0x9C00) + { + int w = ((x->value >> 9) & 0x1); + if (w) + return 1; + } + + return 0; +} + static INSTR_T gen_multi_instr_1 (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2) { @@ -400,6 +430,9 @@ gen_multi_instr_1 (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2) yyerror ("anomaly 05000074 - Multi-Issue Instruction with \ dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported"); + if (is_store (dsp16_grp1) && is_store (dsp16_grp2)) + yyerror ("Only one instruction in multi-issue instruction can be a store"); + return bfin_gen_multi_instr (dsp32, dsp16_grp1, dsp16_grp2); }