From: Michael Meissner <meissner@linux.ibm.com>
Date: Thu, 28 Nov 2019 00:11:28 +0000 (+0000)
Subject: Reformat movdi_internal64.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=db3e062515e7ff41afa1360c61ff7ff9ccbd8414;p=gcc.git

Reformat movdi_internal64.

2019-11-26  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/rs6000.md (movdi_internal64): Reformat.

From-SVN: r278788
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 421507eb8b8..857c06917a4 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,6 +1,7 @@
 2019-11-27  Michael Meissner  <meissner@linux.ibm.com>
 
 	* config/rs6000/rs6000.md (movsi_internal): Reformat.
+	(movdi_internal64): Reformat.
 
 2019-11-27  Peter Bergner <bergner@linux.ibm.com>
 
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 5e939cd3791..876dfe3e959 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -8827,24 +8827,33 @@
   DONE;
 })
 
-;;              GPR store  GPR load   GPR move   GPR li     GPR lis     GPR #
-;;              FPR store  FPR load   FPR move   AVX store  AVX store   AVX load
-;;              AVX load   VSX move   P9 0       P9 -1      AVX 0/-1    VSX 0
-;;              VSX -1     P9 const   AVX const  From SPR   To SPR      SPR<->SPR
-;;              VSX->GPR   GPR->VSX
+;;		GPR store  GPR load   GPR move
+;;		GPR li     GPR lis    GPR #
+;;		FPR store  FPR load   FPR move
+;;		AVX store  AVX store  AVX load   AVX load   VSX move
+;;		P9 0       P9 -1      AVX 0/-1   VSX 0      VSX -1
+;;		P9 const   AVX const
+;;		From SPR   To SPR     SPR<->SPR
+;;		VSX->GPR   GPR->VSX
 (define_insn "*movdi_internal64"
   [(set (match_operand:DI 0 "nonimmediate_operand"
-               "=YZ,       r,         r,         r,         r,          r,
-                m,         ^d,        ^d,        wY,        Z,          $v,
-                $v,        ^wa,       wa,        wa,        v,          wa,
-                wa,        v,         v,         r,         *h,         *h,
-                ?r,        ?wa")
+		"=YZ,       r,          r,
+		r,          r,          r,
+		m,          ^d,         ^d,
+		wY,         Z,          $v,         $v,         ^wa,
+		wa,         wa,         v,          wa,         wa,
+		v,          v,
+		r,          *h,         *h,
+		?r,         ?wa")
 	(match_operand:DI 1 "input_operand"
-               "r,         YZ,        r,         I,         L,          nF,
-                ^d,        m,         ^d,        ^v,        $v,         wY,
-                Z,         ^wa,       Oj,        wM,        OjwM,       Oj,
-                wM,        wS,        wB,        *h,        r,          0,
-                wa,        r"))]
+		"r,         YZ,         r,
+		I,          L,          nF,
+		^d,         m,          ^d,
+		^v,         $v,         wY,         Z,          ^wa,
+		Oj,         wM,         OjwM,       Oj,         wM,
+		wS,         wB,
+		*h,         r,          0,
+		wa,         r"))]
   "TARGET_POWERPC64
    && (gpc_reg_operand (operands[0], DImode)
        || gpc_reg_operand (operands[1], DImode))"
@@ -8876,24 +8885,33 @@
    mfvsrd %0,%x1
    mtvsrd %x0,%1"
   [(set_attr "type"
-               "store,      load,	*,         *,         *,         *,
-                fpstore,    fpload,     fpsimple,  fpstore,   fpstore,   fpload,
-                fpload,     veclogical, vecsimple, vecsimple, vecsimple, veclogical,
-                veclogical, vecsimple,  vecsimple, mfjmpr,    mtjmpr,    *,
-                mftgpr,    mffgpr")
+		"store,      load,       *,
+		*,           *,          *,
+		fpstore,     fpload,     fpsimple,
+		fpstore,     fpstore,    fpload,     fpload,     veclogical,
+		vecsimple,   vecsimple,  vecsimple,  veclogical, veclogical,
+		vecsimple,   vecsimple,
+		mfjmpr,      mtjmpr,     *,
+		mftgpr,      mffgpr")
    (set_attr "size" "64")
    (set_attr "length"
-               "*,         *,         *,         *,         *,          20,
-                *,         *,         *,         *,         *,          *,
-                *,         *,         *,         *,         *,          *,
-                *,         8,         *,         *,         *,          *,
-                *,         *")
+		"*,         *,          *,
+		*,          *,          20,
+		*,          *,          *,
+		*,          *,          *,          *,          *,
+		*,          *,          *,          *,          *,
+		8,          *,
+		*,          *,          *,
+		*,          *")
    (set_attr "isa"
-               "*,         *,         *,         *,         *,          *,
-                *,         *,         *,         p9v,       p7v,        p9v,
-                p7v,       *,         p9v,       p9v,       p7v,        *,
-                *,         p7v,       p7v,       *,         *,          *,
-                p8v,       p8v")])
+		"*,         *,          *,
+		*,          *,          *,
+		*,          *,          *,
+		p9v,        p7v,        p9v,        p7v,        *,
+		p9v,        p9v,        p7v,        *,          *,
+		p7v,        p7v,
+		*,          *,          *,
+		p8v,        p8v")])
 
 ; Some DImode loads are best done as a load of -1 followed by a mask
 ; instruction.