From: Wei Song <wsong83@gmail.com>
Date: Mon, 13 Apr 2015 15:35:13 +0000 (+0100)
Subject: fix cache line index offset in cachesim.cc
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=db428184208c7a57052d4d7cc994f1e4b3664969;p=riscv-isa-sim.git

fix cache line index offset in cachesim.cc
---

diff --git a/riscv/cachesim.cc b/riscv/cachesim.cc
index 9a11187..90ab5be 100644
--- a/riscv/cachesim.cc
+++ b/riscv/cachesim.cc
@@ -45,7 +45,7 @@ void cache_sim_t::init()
     help();
 
   idx_shift = 0;
-  for (size_t x = linesz; x; x >>= 1)
+  for (size_t x = linesz; x>1; x >>= 1)
     idx_shift++;
 
   tags = new uint64_t[sets*ways]();