From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 6 Nov 2018 05:01:09 +0000 (+0000)
Subject: add TODO on vector config state as a "stack"
X-Git-Tag: convert-csv-opcode-to-binary~4856
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=db4853ef3f40ddb6a60c40cd5830b3cfdc4ca7a0;p=libreriscv.git

add TODO on vector config state as a "stack"
---

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index 65c5d43db..3d2fd0803 100644
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -2157,4 +2157,11 @@ TODO: update elwidth to be default / 8 / 16 / 32
 TODO: document different lengths for INT / FP regfiles, and provide
 as part of info register. 00=32, 01=64, 10=128, 11=reserved.
 
+---
+
+push/pop of vector config state:
+<https://groups.google.com/d/msg/comp.arch/bGBeaNjAKvc/z2d_cST7AgAJ>
 
+when Bank in CFG is altered, shift the "addressing" of Reg and
+Pred CSRs to match.  i.e. treat the Reg and Pred CSRs as a
+"mini stack".