From: Nanley Chery Date: Sat, 28 Mar 2020 00:15:51 +0000 (-0700) Subject: intel: Add ISL_AUX_USAGE_GEN12_CCS_E X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=db5d98cde82b1430dd1dabe36dcfefa6aef5484c;p=mesa.git intel: Add ISL_AUX_USAGE_GEN12_CCS_E Add a new aux usage which more accurately describes the behavior of CCS_E on gen12. On this platform, writes using the 3D engine are either compressed or substituted with fast-cleared blocks. Reviewed-by: Kenneth Graunke Part-of: --- diff --git a/src/gallium/drivers/iris/iris_resource.c b/src/gallium/drivers/iris/iris_resource.c index 232494a9c1f..0b142bb7906 100644 --- a/src/gallium/drivers/iris/iris_resource.c +++ b/src/gallium/drivers/iris/iris_resource.c @@ -569,6 +569,8 @@ iris_resource_configure_aux(struct iris_screen *screen, */ initial_state = ISL_AUX_STATE_CLEAR; break; + case ISL_AUX_USAGE_GEN12_CCS_E: + unreachable("Driver unprepared to handle this aux_usage."); case ISL_AUX_USAGE_CCS_D: case ISL_AUX_USAGE_CCS_E: case ISL_AUX_USAGE_STC_CCS: diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c index 4da1139199c..3aac0abf274 100644 --- a/src/intel/blorp/blorp_blit.c +++ b/src/intel/blorp/blorp_blit.c @@ -2664,6 +2664,7 @@ blorp_copy(struct blorp_batch *batch, params.src.aux_usage == ISL_AUX_USAGE_MCS || params.src.aux_usage == ISL_AUX_USAGE_MCS_CCS || params.src.aux_usage == ISL_AUX_USAGE_CCS_E || + params.src.aux_usage == ISL_AUX_USAGE_GEN12_CCS_E || params.src.aux_usage == ISL_AUX_USAGE_STC_CCS); if (isl_aux_usage_has_hiz(params.src.aux_usage)) { @@ -2679,9 +2680,11 @@ blorp_copy(struct blorp_batch *batch, */ params.src.view.format = params.dst.surf.format; params.dst.view.format = params.dst.surf.format; - } else if (params.dst.aux_usage == ISL_AUX_USAGE_CCS_E) { + } else if (params.dst.aux_usage == ISL_AUX_USAGE_CCS_E || + params.dst.aux_usage == ISL_AUX_USAGE_GEN12_CCS_E) { params.dst.view.format = get_ccs_compatible_copy_format(dst_fmtl); - if (params.src.aux_usage == ISL_AUX_USAGE_CCS_E) { + if (params.src.aux_usage == ISL_AUX_USAGE_CCS_E || + params.src.aux_usage == ISL_AUX_USAGE_GEN12_CCS_E) { params.src.view.format = get_ccs_compatible_copy_format(src_fmtl); } else if (src_fmtl->bpb == dst_fmtl->bpb) { params.src.view.format = params.dst.view.format; @@ -2689,7 +2692,8 @@ blorp_copy(struct blorp_batch *batch, params.src.view.format = get_copy_format_for_bpb(isl_dev, src_fmtl->bpb); } - } else if (params.src.aux_usage == ISL_AUX_USAGE_CCS_E) { + } else if (params.src.aux_usage == ISL_AUX_USAGE_CCS_E || + params.src.aux_usage == ISL_AUX_USAGE_GEN12_CCS_E) { params.src.view.format = get_ccs_compatible_copy_format(src_fmtl); if (src_fmtl->bpb == dst_fmtl->bpb) { params.dst.view.format = params.src.view.format; diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index 80c801370d2..98b55164fac 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -611,6 +611,13 @@ enum isl_aux_usage { */ ISL_AUX_USAGE_CCS_E, + /** The auxiliary surface provides full lossless color compression on + * Gen12. + * + * @invariant isl_surf::samples == 1 + */ + ISL_AUX_USAGE_GEN12_CCS_E, + /** The auxiliary surface provides full lossless media color compression * * @invariant isl_surf::samples == 1 @@ -1803,6 +1810,7 @@ isl_aux_usage_has_ccs(enum isl_aux_usage usage) { return usage == ISL_AUX_USAGE_CCS_D || usage == ISL_AUX_USAGE_CCS_E || + usage == ISL_AUX_USAGE_GEN12_CCS_E || usage == ISL_AUX_USAGE_MC || usage == ISL_AUX_USAGE_HIZ_CCS_WT || usage == ISL_AUX_USAGE_HIZ_CCS || @@ -1864,7 +1872,8 @@ isl_drm_modifier_get_default_aux_state(uint64_t modifier) if (!mod_info || mod_info->aux_usage == ISL_AUX_USAGE_NONE) return ISL_AUX_STATE_AUX_INVALID; - assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E); + assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E || + mod_info->aux_usage == ISL_AUX_USAGE_GEN12_CCS_E); return mod_info->supports_clear_color ? ISL_AUX_STATE_COMPRESSED_CLEAR : ISL_AUX_STATE_COMPRESSED_NO_CLEAR; } diff --git a/src/intel/isl/isl_aux_info.c b/src/intel/isl/isl_aux_info.c index 6d12f3f4e55..d771b15b604 100644 --- a/src/intel/isl/isl_aux_info.c +++ b/src/intel/isl/isl_aux_info.c @@ -49,6 +49,11 @@ enum write_behavior { /* Writes using the 3D engine are compressed. */ WRITES_COMPRESS, + /* Writes using the 3D engine are either compressed or substituted with + * fast-cleared blocks. + */ + WRITES_COMPRESS_CLEAR, + /* Writes implicitly fully resolve the compression block and write the data * uncompressed into the main surface. The resolved aux blocks are * ambiguated and left in the pass-through state. @@ -87,6 +92,7 @@ static const struct aux_usage_info info[] = { AUX( COMPRESS, Y, Y, Y, x, MCS) AUX( COMPRESS, Y, Y, Y, x, MCS_CCS) AUX( COMPRESS, Y, Y, Y, Y, CCS_E) + AUX( COMPRESS_CLEAR, Y, Y, Y, Y, GEN12_CCS_E) AUX(RESOLVE_AMBIGUATE, x, Y, x, Y, CCS_D) AUX(RESOLVE_AMBIGUATE, Y, x, x, Y, MC) AUX( COMPRESS, Y, x, x, Y, STC_CCS) @@ -213,24 +219,29 @@ isl_aux_state_transition_write(enum isl_aux_state initial_state, assert(isl_aux_state_has_valid_aux(initial_state)); assert(aux_state_possible(initial_state, usage)); assert(info[usage].write_behavior == WRITES_COMPRESS || + info[usage].write_behavior == WRITES_COMPRESS_CLEAR || info[usage].write_behavior == WRITES_RESOLVE_AMBIGUATE); if (full_surface) { return info[usage].write_behavior == WRITES_COMPRESS ? - ISL_AUX_STATE_COMPRESSED_NO_CLEAR : ISL_AUX_STATE_PASS_THROUGH; + ISL_AUX_STATE_COMPRESSED_NO_CLEAR : + info[usage].write_behavior == WRITES_COMPRESS_CLEAR ? + ISL_AUX_STATE_COMPRESSED_CLEAR : ISL_AUX_STATE_PASS_THROUGH; } switch (initial_state) { case ISL_AUX_STATE_CLEAR: case ISL_AUX_STATE_PARTIAL_CLEAR: - return info[usage].write_behavior == WRITES_COMPRESS ? - ISL_AUX_STATE_COMPRESSED_CLEAR : ISL_AUX_STATE_PARTIAL_CLEAR; + return info[usage].write_behavior == WRITES_RESOLVE_AMBIGUATE ? + ISL_AUX_STATE_PARTIAL_CLEAR : ISL_AUX_STATE_COMPRESSED_CLEAR; case ISL_AUX_STATE_RESOLVED: case ISL_AUX_STATE_PASS_THROUGH: + case ISL_AUX_STATE_COMPRESSED_NO_CLEAR: return info[usage].write_behavior == WRITES_COMPRESS ? - ISL_AUX_STATE_COMPRESSED_NO_CLEAR : initial_state; + ISL_AUX_STATE_COMPRESSED_NO_CLEAR : + info[usage].write_behavior == WRITES_COMPRESS_CLEAR ? + ISL_AUX_STATE_COMPRESSED_CLEAR : initial_state; case ISL_AUX_STATE_COMPRESSED_CLEAR: - case ISL_AUX_STATE_COMPRESSED_NO_CLEAR: case ISL_AUX_STATE_AUX_INVALID: return initial_state; #ifdef IN_UNIT_TEST diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index a3dc15708b0..e44d5f74137 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -90,6 +90,7 @@ static const uint32_t isl_to_gen_multisample_layout[] = { static const uint32_t isl_to_gen_aux_mode[] = { [ISL_AUX_USAGE_NONE] = AUX_NONE, [ISL_AUX_USAGE_MCS] = AUX_CCS_E, + [ISL_AUX_USAGE_GEN12_CCS_E] = AUX_CCS_E, [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E, [ISL_AUX_USAGE_HIZ_CCS_WT] = AUX_CCS_E, [ISL_AUX_USAGE_MCS_CCS] = AUX_MCS_LCE, @@ -589,6 +590,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, if (GEN_GEN >= 12) { assert(info->aux_usage == ISL_AUX_USAGE_MCS || info->aux_usage == ISL_AUX_USAGE_CCS_E || + info->aux_usage == ISL_AUX_USAGE_GEN12_CCS_E || info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT || info->aux_usage == ISL_AUX_USAGE_MCS_CCS || info->aux_usage == ISL_AUX_USAGE_STC_CCS); diff --git a/src/intel/isl/tests/isl_aux_info_test.cpp b/src/intel/isl/tests/isl_aux_info_test.cpp index d31d0434fdd..f096c54a41d 100644 --- a/src/intel/isl/tests/isl_aux_info_test.cpp +++ b/src/intel/isl/tests/isl_aux_info_test.cpp @@ -376,6 +376,23 @@ TEST(StateTransitionWrite, WritesCompress) { E(AUX_INVALID, STC_CCS, true, ASSERT); } +TEST(StateTransitionWrite, WritesCompressClear) { + E(CLEAR, GEN12_CCS_E, false, COMPRESSED_CLEAR); + E(CLEAR, GEN12_CCS_E, true, COMPRESSED_CLEAR); + E(PARTIAL_CLEAR, GEN12_CCS_E, false, COMPRESSED_CLEAR); + E(PARTIAL_CLEAR, GEN12_CCS_E, true, COMPRESSED_CLEAR); + E(COMPRESSED_CLEAR, GEN12_CCS_E, false, COMPRESSED_CLEAR); + E(COMPRESSED_CLEAR, GEN12_CCS_E, true, COMPRESSED_CLEAR); + E(COMPRESSED_NO_CLEAR, GEN12_CCS_E, false, COMPRESSED_CLEAR); + E(COMPRESSED_NO_CLEAR, GEN12_CCS_E, true, COMPRESSED_CLEAR); + E(RESOLVED, GEN12_CCS_E, false, COMPRESSED_CLEAR); + E(RESOLVED, GEN12_CCS_E, true, COMPRESSED_CLEAR); + E(PASS_THROUGH, GEN12_CCS_E, false, COMPRESSED_CLEAR); + E(PASS_THROUGH, GEN12_CCS_E, true, COMPRESSED_CLEAR); + E(AUX_INVALID, GEN12_CCS_E, false, ASSERT); + E(AUX_INVALID, GEN12_CCS_E, true, ASSERT); +} + TEST(StateTransitionWrite, WritesResolveAmbiguate) { E(CLEAR, CCS_D, false, PARTIAL_CLEAR); E(CLEAR, CCS_D, true, PASS_THROUGH);