From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Mon, 10 Oct 2016 20:32:25 +0000 (-0700)
Subject: Don't force load trigger timing to After
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=db6051f2001243e5132f224ece06753aff85748d;p=riscv-isa-sim.git

Don't force load trigger timing to After

Allow the CSR writer to make the choice.

@timsifive @colinschmidt this fixes the failing rv64mi-p-breakpoint test.
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 47a3a66..f3764ae 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -437,8 +437,6 @@ void processor_t::set_csr(int which, reg_t val)
         // Assume we're here because of csrw.
         if (mc->execute)
           mc->timing = 0;
-        if (mc->load)
-          mc->timing = 1;
         trigger_updated();
       }
       break;