From: Jason Ekstrand Date: Fri, 15 Dec 2017 06:10:10 +0000 (-0800) Subject: i965/fs: Reset the register file to VGRF in lower_integer_multiplication X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=db682b8f0eafd3b9d58e736e9e2f520943a89942;p=mesa.git i965/fs: Reset the register file to VGRF in lower_integer_multiplication 18fde36ced4279f2577097a1a7d31b55f2f5f141 changed the way temporary registers were allocated in lower_integer_multiplication so that we allocate regs_written(inst) space and keep the stride of the original destination register. This was to ensure that any MUL which originally followed the CHV/BXT integer multiply regioning restrictions would continue to follow those restrictions even after lowering. This works fine except that I forgot to reset the register file to VGRF so, even though they were assigned a number from alloc.allocate(), they had the wrong register file. This caused some GLES 3.0 CTS tests to start failing on Sandy Bridge due to attempted reads from the MRF: ES3-CTS.functional.shaders.precision.int.highp_mul_fragment.snbm64 ES3-CTS.functional.shaders.precision.int.mediump_mul_fragment.snbm64 ES3-CTS.functional.shaders.precision.int.lowp_mul_fragment.snbm64 ES3-CTS.functional.shaders.precision.uint.highp_mul_fragment.snbm64 ES3-CTS.functional.shaders.precision.uint.mediump_mul_fragment.snbm64 ES3-CTS.functional.shaders.precision.uint.lowp_mul_fragment.snbm64 This commit remedies this problem by, instead of copying inst->dst and overwriting nr, just make a new register and set the region to match inst->dst. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103626 Fixes: 18fde36ced4279f2577097a1a7d31b55f2f5f141 Cc: "17.3" Reviewed-by: Matt Turner --- diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index faf3a52c26d..09adcbc2df1 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -3640,13 +3640,18 @@ fs_visitor::lower_integer_multiplication() regions_overlap(inst->dst, inst->size_written, inst->src[1], inst->size_read(1))) { needs_mov = true; - low.nr = alloc.allocate(regs_written(inst)); - low.offset = low.offset % REG_SIZE; + /* Get a new VGRF but keep the same stride as inst->dst */ + low = fs_reg(VGRF, alloc.allocate(regs_written(inst)), + inst->dst.type); + low.stride = inst->dst.stride; + low.offset = inst->dst.offset % REG_SIZE; } - fs_reg high = inst->dst; - high.nr = alloc.allocate(regs_written(inst)); - high.offset = high.offset % REG_SIZE; + /* Get a new VGRF but keep the same stride as inst->dst */ + fs_reg high(VGRF, alloc.allocate(regs_written(inst)), + inst->dst.type); + high.stride = inst->dst.stride; + high.offset = inst->dst.offset % REG_SIZE; if (devinfo->gen >= 7) { if (inst->src[1].file == IMM) {