From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 24 Jun 2019 21:28:56 +0000 (-0700)
Subject: Reduce number of decomposed muxes during techmap
X-Git-Tag: working-ls180~1208^2~84
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=db6a0b72b24022eacc84dba8b117dfb193b8d4c1;p=yosys.git

Reduce number of decomposed muxes during techmap
---

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 85f174d3d..6d9860b95 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -225,7 +225,7 @@ module \$__XILINX_SHIFTX (A, B, Y);
     else if (A_WIDTH <= 2 ** 4) begin
       localparam a_width0 = 2 ** 2;
       localparam num_mux8 = A_WIDTH / a_width0;
-      localparam a_widthN = A_WIDTH - num_mux8*a_width0;
+      localparam a_widthN = A_WIDTH % a_width0;
       wire [a_width0-1:0] T;
       for (i = 0; i < a_width0; i++)
         if (i < num_mux8)
@@ -243,20 +243,17 @@ module \$__XILINX_SHIFTX (A, B, Y);
     else begin
       localparam a_width0 = 2 ** 4;
       localparam num_mux16 = A_WIDTH / a_width0;
-      localparam a_widthN = A_WIDTH - num_mux16*a_width0;
-      wire [a_width0-1:0] T;
-      for (i = 0; i < a_width0; i++)
-        if (i < num_mux16)
-          \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i]));
-        else if (i == num_mux16 && a_widthN > 0) begin
-          if (a_widthN > 1)
-            \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1-:a_widthN]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
-          else
-            assign T[i] = A[A_WIDTH-1];
-        end
+      localparam a_widthN = A_WIDTH % a_width0;
+      wire [num_mux16 + (a_widthN > 0 ? 1 : 0) - 1:0] T;
+      for (i = 0; i < num_mux16; i++)
+        \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i]));
+      if (a_widthN > 0) begin
+        if (a_widthN > 1)
+          \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1-:a_widthN]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[num_mux16]));
         else
-          assign T[i] = 1'bx;
-      \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
+          assign T[num_mux16] = A[A_WIDTH-1];
+      end
+      \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(num_mux16 + (a_widthN > 0 ? 1 : 0)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
     end
   endgenerate
 endmodule