From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 25 Jul 2020 14:34:16 +0000 (+0100)
Subject: add div compunit test
X-Git-Tag: semi_working_ecp5~548
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=db6b993384779aa8e4580b1391ac9d3b384fae66;p=soc.git

add div compunit test
---

diff --git a/src/soc/fu/compunits/test/test_div_compunit.py b/src/soc/fu/compunits/test/test_div_compunit.py
new file mode 100644
index 00000000..bce3216a
--- /dev/null
+++ b/src/soc/fu/compunits/test/test_div_compunit.py
@@ -0,0 +1,58 @@
+import unittest
+from soc.decoder.power_enums import (XER_bits, Function)
+
+from soc.fu.div.test.test_pipe_caller import get_cu_inputs
+from soc.fu.div.test.test_pipe_caller import DivTestCases  # creates the tests
+
+from soc.fu.test.common import ALUHelpers
+from soc.fu.compunits.compunits import DivFunctionUnit
+from soc.fu.compunits.test.test_compunit import TestRunner
+from soc.config.endian import bigendian
+
+
+class DivTestRunner(TestRunner):
+    def __init__(self, test_data):
+        super().__init__(test_data, DivFunctionUnit, self,
+                         Function.DIV, bigendian)
+
+    def get_cu_inputs(self, dec2, sim):
+        """naming (res) must conform to DivFunctionUnit input regspec
+        """
+        res = yield from get_cu_inputs(dec2, sim)
+        return res
+
+    def check_cu_outputs(self, res, dec2, sim, alu, code):
+        """naming (res) must conform to DivFunctionUnit output regspec
+        """
+
+        rc = yield dec2.e.do.rc.data
+        op = yield dec2.e.do.insn_type
+        cridx_ok = yield dec2.e.write_cr.ok
+        cridx = yield dec2.e.write_cr.data
+
+        print("check extra output", repr(code), cridx_ok, cridx)
+
+        if rc:
+            self.assertEqual(cridx_ok, 1, code)
+            self.assertEqual(cridx, 0, code)
+
+        sim_o = {}
+
+        yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
+        yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
+        yield from ALUHelpers.get_wr_sim_xer_ov(sim_o, sim, alu, dec2)
+        yield from ALUHelpers.get_wr_sim_xer_so(sim_o, sim, alu, dec2)
+
+        ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
+        ALUHelpers.check_xer_ov(self, res, sim_o, code)
+        ALUHelpers.check_int_o(self, res, sim_o, code)
+        ALUHelpers.check_xer_so(self, res, sim_o, code)
+
+
+if __name__ == "__main__":
+    unittest.main(exit=False)
+    suite = unittest.TestSuite()
+    suite.addTest(DivTestRunner(DivTestCases.test_data))
+
+    runner = unittest.TextTestRunner()
+    runner.run(suite)