From: lkcl <lkcl@web>
Date: Wed, 4 Aug 2021 15:04:46 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~502
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=db6ee0fb304313b995093146fc5a8ef31b66c696;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 73dbafb7e..9a795d9e8 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -136,6 +136,20 @@ Available options to combine:
 * `ALL` or `ANY` behaviour corresponding to `AND` of all tests and
   `OR` of all tests, respectively.
 
+In addition to the above, it is necessary to select whether, in `svstep`
+mode, the Vector CR Field is to be overwritten or not: in some cases
+it is useful to know but in others all that is needed is the branch itself.
+In the case of `sv.bc` there is no additional bitspace so the ``AA`
+field is re-interpreted instead to be `Rc`. For `sv.bclr`, there is free
+bitspace and so bit 16 has been chosen as `Rc`.
+
+**These interpretations are only available for sv.bc, they are NOT
+available for Power ISA v3.0B** i.e. only when embedded in an SVP64
+Prefix Context do these and all other parts of this specification
+apply.  To repeat: **Standard Scalar v3.0B Branch is in
+absolutely no way impacted or altered in any way shape or form by
+the SVP64 variant of the same**
+
 Pseudocode for Rc in sv.bc
 
 ```