From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 13 Feb 2017 15:55:25 +0000 (+0100)
Subject: Fix techmap for inout ports connected to inout ports
X-Git-Tag: yosys-0.8~495
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=db7314bc02b4e8b1827993cd844eac9c7070579f;p=yosys.git

Fix techmap for inout ports connected to inout ports
---

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 6784f48c3..b351d3be8 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -305,10 +305,15 @@ struct TechmapWorker
 				// approach that yields nicer outputs:
 				// replace internal wires that are connected to external wires
 
-				if (w->port_output)
+				if (w->port_output && !w->port_input) {
 					port_signal_map.add(c.second, c.first);
-				else
+				} else
+				if (!w->port_output && w->port_input) {
 					port_signal_map.add(c.first, c.second);
+				} else {
+					module->connect(c);
+					extra_connect = SigSig();
+				}
 
 				for (auto &attr : w->attributes) {
 					if (attr.first == "\\src")