From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Tue, 6 Mar 2012 17:33:44 +0000 (+0100)
Subject: fhdl: register memory objects with namespace
X-Git-Tag: 24jan2021_ls180~2099^2~989
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=db8f8bf2e375ddee9f5b3fdb376a1c2545e0a62d;p=litex.git

fhdl: register memory objects with namespace
---

diff --git a/migen/fhdl/namer.py b/migen/fhdl/namer.py
index c2ef318c..55a79c3e 100644
--- a/migen/fhdl/namer.py
+++ b/migen/fhdl/namer.py
@@ -1,52 +1,6 @@
-import inspect
 from itertools import combinations
-from opcode import opname
 
-def get_var_name(frame):
-	code = frame.f_code
-	call_index = frame.f_lasti
-	if opname[code.co_code[call_index]] != "CALL_FUNCTION":
-		return None
-	index = call_index+3
-	while True:
-		opc = opname[code.co_code[index]]
-		if opc == "STORE_NAME" or opc == "STORE_ATTR":
-			name_index = int(code.co_code[index+1])
-			return code.co_names[name_index]
-		elif opc == "STORE_FAST":
-			name_index = int(code.co_code[index+1])
-			return code.co_varnames[name_index]
-		elif opc == "STORE_DEREF":
-			name_index = int(code.co_code[index+1])
-			return code.co_cellvars[name_index]
-		elif opc == "LOAD_GLOBAL" or opc == "LOAD_ATTR" or opc == "LOAD_FAST":
-			index += 3
-		elif opc == "DUP_TOP":
-			index += 1
-		else:
-			return None
-
-def trace_back(name=None):
-	l = []
-	frame = inspect.currentframe().f_back.f_back
-	while frame is not None:
-		try:
-			obj = frame.f_locals["self"]
-		except KeyError:
-			obj = None
-		if obj is not None and hasattr(obj, "__del__"):
-			obj = None
-		if obj is None:
-			modules = frame.f_globals["__name__"]
-			modules = modules.split(".")
-			obj = modules[len(modules)-1]
-		
-		if name is None:
-			name = get_var_name(frame)
-		l.insert(0, (obj, name))
-		name = None
-		frame = frame.f_back
-	return l
+from migen.fhdl.structure import *
 
 class _StepNamer():
 	def __init__(self):
@@ -160,10 +114,13 @@ class Namespace:
 		self.pnd = pnd
 	
 	def get_name(self, sig):
-		if sig.name_override is not None:
-			sig_name = sig.name_override
+		if isinstance(sig, Memory):
+			sig_name = "mem"
 		else:
-			sig_name = self.pnd[sig]
+			if sig.name_override is not None:
+				sig_name = sig.name_override
+			else:
+				sig_name = self.pnd[sig]
 		try:
 			n = self.sigs[sig]
 		except KeyError:
diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index 45f97705..21e5cb0e 100644
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -2,7 +2,7 @@ import math
 import inspect
 import re
 
-from migen.fhdl import namer
+from migen.fhdl import tracer
 
 def bits_for(n):
 	if isinstance(n, Constant):
@@ -143,7 +143,7 @@ class Signal(Value):
 		self.variable = variable
 		self.reset = Constant(reset, bv)
 		self.name_override = name_override
-		self.backtrace = namer.trace_back(name)
+		self.backtrace = tracer.trace_back(name)
 
 	def __hash__(self):
 		return id(self)
diff --git a/migen/fhdl/tracer.py b/migen/fhdl/tracer.py
new file mode 100644
index 00000000..c363eadd
--- /dev/null
+++ b/migen/fhdl/tracer.py
@@ -0,0 +1,48 @@
+import inspect
+from opcode import opname
+
+def get_var_name(frame):
+	code = frame.f_code
+	call_index = frame.f_lasti
+	if opname[code.co_code[call_index]] != "CALL_FUNCTION":
+		return None
+	index = call_index+3
+	while True:
+		opc = opname[code.co_code[index]]
+		if opc == "STORE_NAME" or opc == "STORE_ATTR":
+			name_index = int(code.co_code[index+1])
+			return code.co_names[name_index]
+		elif opc == "STORE_FAST":
+			name_index = int(code.co_code[index+1])
+			return code.co_varnames[name_index]
+		elif opc == "STORE_DEREF":
+			name_index = int(code.co_code[index+1])
+			return code.co_cellvars[name_index]
+		elif opc == "LOAD_GLOBAL" or opc == "LOAD_ATTR" or opc == "LOAD_FAST":
+			index += 3
+		elif opc == "DUP_TOP":
+			index += 1
+		else:
+			return None
+
+def trace_back(name=None):
+	l = []
+	frame = inspect.currentframe().f_back.f_back
+	while frame is not None:
+		try:
+			obj = frame.f_locals["self"]
+		except KeyError:
+			obj = None
+		if obj is not None and hasattr(obj, "__del__"):
+			obj = None
+		if obj is None:
+			modules = frame.f_globals["__name__"]
+			modules = modules.split(".")
+			obj = modules[len(modules)-1]
+		
+		if name is None:
+			name = get_var_name(frame)
+		l.insert(0, (obj, name))
+		name = None
+		frame = frame.f_back
+	return l
diff --git a/migen/fhdl/verilog_mem_behavioral.py b/migen/fhdl/verilog_mem_behavioral.py
index bb3f437d..59fb86f8 100644
--- a/migen/fhdl/verilog_mem_behavioral.py
+++ b/migen/fhdl/verilog_mem_behavioral.py
@@ -5,9 +5,8 @@ def handler(memory, ns, clk):
 	gn = ns.get_name
 	adrbits = bits_for(memory.depth-1)
 	
-	storage = Signal(name_override="mem")
 	r += "reg [" + str(memory.width-1) + ":0] " \
-		+ gn(storage) \
+		+ gn(memory) \
 		+ "[0:" + str(memory.depth-1) + "];\n"
 
 	adr_regs = {}
@@ -35,15 +34,15 @@ def handler(memory, ns, clk):
 					M = (i+1)*port.we_granularity-1
 					sl = "[" + str(M) + ":" + str(m) + "]"
 					r += "\tif (" + gn(port.we) + "[" + str(i) + "])\n"
-					r += "\t\t" + gn(storage) + "[" + gn(port.adr) + "]" + sl + " <= " + gn(port.dat_w) + sl + ";\n"
+					r += "\t\t" + gn(memory) + "[" + gn(port.adr) + "]" + sl + " <= " + gn(port.dat_w) + sl + ";\n"
 			else:
 				r += "\tif (" + gn(port.we) + ")\n"
-				r += "\t\t" + gn(storage) + "[" + gn(port.adr) + "] <= " + gn(port.dat_w) + ";\n"
+				r += "\t\t" + gn(memory) + "[" + gn(port.adr) + "] <= " + gn(port.dat_w) + ";\n"
 		if not port.async_read:
 			if port.mode == WRITE_FIRST and port.we is not None:
 				rd = "\t" + gn(adr_regs[id(port)]) + " <= " + gn(port.adr) + ";\n"
 			else:
-				bassign = gn(data_regs[id(port)]) + " <= " + gn(storage) + "[" + gn(port.adr) + "];\n"
+				bassign = gn(data_regs[id(port)]) + " <= " + gn(memory) + "[" + gn(port.adr) + "];\n"
 				if port.mode == READ_FIRST or port.we is None:
 					rd = "\t" + bassign
 				elif port.mode == NO_CHANGE:
@@ -58,10 +57,10 @@ def handler(memory, ns, clk):
 	
 	for port in memory.ports:
 		if port.async_read:
-			r += "assign " + gn(port.dat_r) + " = " + gn(storage) + "[" + gn(port.adr) + "];\n"
+			r += "assign " + gn(port.dat_r) + " = " + gn(memory) + "[" + gn(port.adr) + "];\n"
 		else:
 			if port.mode == WRITE_FIRST and port.we is not None:
-				r += "assign " + gn(port.dat_r) + " = " + gn(storage) + "[" + gn(adr_regs[id(port)]) + "];\n"
+				r += "assign " + gn(port.dat_r) + " = " + gn(memory) + "[" + gn(adr_regs[id(port)]) + "];\n"
 			else:
 				r += "assign " + gn(port.dat_r) + " = " + gn(data_regs[id(port)]) + ";\n"
 	r += "\n"
@@ -69,7 +68,7 @@ def handler(memory, ns, clk):
 	if memory.init is not None:
 		r += "initial begin\n"
 		for i, c in enumerate(memory.init):
-			r += "\t" + gn(storage) + "[" + str(i) + "] <= " + str(memory.width) + "'d" + str(c) + ";\n"
+			r += "\t" + gn(memory) + "[" + str(i) + "] <= " + str(memory.width) + "'d" + str(c) + ";\n"
 		r += "end\n\n"
 	
 	return r