From: Gabe Black <gabeblack@google.com>
Date: Sun, 6 Sep 2020 12:01:48 +0000 (-0700)
Subject: arm: Remove "using namespace ArmISA" from arch/arm/isa_traits.hh.
X-Git-Tag: v20.1.0.0~59
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dba46233950817b4c696781bc3c1891a5b499651;p=gem5.git

arm: Remove "using namespace ArmISA" from arch/arm/isa_traits.hh.

This has been in this file since it was created in 2009. No global "using
namespace ${NAMESPACE}" should ever appear in a .hh file since then that
namespace is "used" in all files that include the .hh, even if they
aren't aware of it or even actively don't want to.

Change-Id: Idb7d7c5b959077eb4905fbb2044aa55959b8f37f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34155
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index f1012be5e..f70b7a71a 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -40,6 +40,8 @@
 
 #include "cpu/reg_class.hh"
 
+using namespace ArmISA;
+
 std::string
 MrsOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 {
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index 9caae0ca4..cfd73b171 100644
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -40,28 +40,28 @@
 
 #include "arch/arm/insts/pred_inst.hh"
 
-class MrsOp : public PredOp
+class MrsOp : public ArmISA::PredOp
 {
   protected:
-    IntRegIndex dest;
+    ArmISA::IntRegIndex dest;
 
-    MrsOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
-            IntRegIndex _dest) :
-        PredOp(mnem, _machInst, __opClass), dest(_dest)
+    MrsOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass,
+            ArmISA::IntRegIndex _dest) :
+        ArmISA::PredOp(mnem, _machInst, __opClass), dest(_dest)
     {}
 
     std::string generateDisassembly(
             Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
-class MsrBase : public PredOp
+class MsrBase : public ArmISA::PredOp
 {
   protected:
     uint8_t byteMask;
 
-    MsrBase(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+    MsrBase(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass,
             uint8_t _byteMask) :
-        PredOp(mnem, _machInst, __opClass), byteMask(_byteMask)
+        ArmISA::PredOp(mnem, _machInst, __opClass), byteMask(_byteMask)
     {}
 
     void printMsrBase(std::ostream &os) const;
@@ -72,8 +72,8 @@ class MsrImmOp : public MsrBase
   protected:
     uint32_t imm;
 
-    MsrImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
-             uint32_t _imm, uint8_t _byteMask) :
+    MsrImmOp(const char *mnem, ArmISA::ExtMachInst _machInst,
+             OpClass __opClass, uint32_t _imm, uint8_t _byteMask) :
         MsrBase(mnem, _machInst, __opClass, _byteMask), imm(_imm)
     {}
 
@@ -84,10 +84,10 @@ class MsrImmOp : public MsrBase
 class MsrRegOp : public MsrBase
 {
   protected:
-    IntRegIndex op1;
+    ArmISA::IntRegIndex op1;
 
-    MsrRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
-             IntRegIndex _op1, uint8_t _byteMask) :
+    MsrRegOp(const char *mnem, ArmISA::ExtMachInst _machInst,
+             OpClass __opClass, ArmISA::IntRegIndex _op1, uint8_t _byteMask) :
         MsrBase(mnem, _machInst, __opClass, _byteMask), op1(_op1)
     {}
 
@@ -95,18 +95,18 @@ class MsrRegOp : public MsrBase
             Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
-class MrrcOp : public PredOp
+class MrrcOp : public ArmISA::PredOp
 {
   protected:
-    MiscRegIndex op1;
-    IntRegIndex dest;
-    IntRegIndex dest2;
-    uint32_t    imm;
+    ArmISA::MiscRegIndex op1;
+    ArmISA::IntRegIndex dest;
+    ArmISA::IntRegIndex dest2;
+    uint32_t imm;
 
-    MrrcOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
-           MiscRegIndex _op1, IntRegIndex _dest, IntRegIndex _dest2,
-           uint32_t _imm) :
-        PredOp(mnem, _machInst, __opClass), op1(_op1), dest(_dest),
+    MrrcOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass,
+           ArmISA::MiscRegIndex _op1, ArmISA::IntRegIndex _dest,
+           ArmISA::IntRegIndex _dest2, uint32_t _imm) :
+        ArmISA::PredOp(mnem, _machInst, __opClass), op1(_op1), dest(_dest),
         dest2(_dest2), imm(_imm)
     {}
 
@@ -114,18 +114,18 @@ class MrrcOp : public PredOp
             Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
-class McrrOp : public PredOp
+class McrrOp : public ArmISA::PredOp
 {
   protected:
-    IntRegIndex op1;
-    IntRegIndex op2;
-    MiscRegIndex dest;
+    ArmISA::IntRegIndex op1;
+    ArmISA::IntRegIndex op2;
+    ArmISA::MiscRegIndex dest;
     uint32_t    imm;
 
-    McrrOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
-           IntRegIndex _op1, IntRegIndex _op2, MiscRegIndex _dest,
-           uint32_t _imm) :
-        PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2),
+    McrrOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass,
+           ArmISA::IntRegIndex _op1, ArmISA::IntRegIndex _op2,
+           ArmISA::MiscRegIndex _dest, uint32_t _imm) :
+        ArmISA::PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2),
         dest(_dest), imm(_imm)
     {}
 
@@ -133,74 +133,76 @@ class McrrOp : public PredOp
             Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
-class ImmOp : public PredOp
+class ImmOp : public ArmISA::PredOp
 {
   protected:
     uint64_t imm;
 
-    ImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+    ImmOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass,
              uint64_t _imm) :
-        PredOp(mnem, _machInst, __opClass), imm(_imm)
+        ArmISA::PredOp(mnem, _machInst, __opClass), imm(_imm)
     {}
 
     std::string generateDisassembly(
             Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
-class RegImmOp : public PredOp
+class RegImmOp : public ArmISA::PredOp
 {
   protected:
-    IntRegIndex dest;
+    ArmISA::IntRegIndex dest;
     uint64_t imm;
 
-    RegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
-             IntRegIndex _dest, uint64_t _imm) :
-        PredOp(mnem, _machInst, __opClass), dest(_dest), imm(_imm)
+    RegImmOp(const char *mnem, ArmISA::ExtMachInst _machInst,
+             OpClass __opClass, ArmISA::IntRegIndex _dest, uint64_t _imm) :
+        ArmISA::PredOp(mnem, _machInst, __opClass), dest(_dest), imm(_imm)
     {}
 
     std::string generateDisassembly(
             Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
-class RegRegOp : public PredOp
+class RegRegOp : public ArmISA::PredOp
 {
   protected:
-    IntRegIndex dest;
-    IntRegIndex op1;
+    ArmISA::IntRegIndex dest;
+    ArmISA::IntRegIndex op1;
 
-    RegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
-             IntRegIndex _dest, IntRegIndex _op1) :
-        PredOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1)
+    RegRegOp(const char *mnem, ArmISA::ExtMachInst _machInst,
+             OpClass __opClass, ArmISA::IntRegIndex _dest,
+             ArmISA::IntRegIndex _op1) :
+        ArmISA::PredOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1)
     {}
 
     std::string generateDisassembly(
             Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
-class RegOp : public PredOp
+class RegOp : public ArmISA::PredOp
 {
   protected:
-    IntRegIndex dest;
+    ArmISA::IntRegIndex dest;
 
-    RegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
-             IntRegIndex _dest) :
-        PredOp(mnem, _machInst, __opClass), dest(_dest)
+    RegOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass,
+             ArmISA::IntRegIndex _dest) :
+        ArmISA::PredOp(mnem, _machInst, __opClass), dest(_dest)
     {}
 
     std::string generateDisassembly(
             Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
-class RegImmRegOp : public PredOp
+class RegImmRegOp : public ArmISA::PredOp
 {
   protected:
-    IntRegIndex dest;
+    ArmISA::IntRegIndex dest;
     uint64_t imm;
-    IntRegIndex op1;
+    ArmISA::IntRegIndex op1;
 
-    RegImmRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
-                IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1) :
-        PredOp(mnem, _machInst, __opClass),
+    RegImmRegOp(const char *mnem, ArmISA::ExtMachInst _machInst,
+                OpClass __opClass, ArmISA::IntRegIndex _dest, uint64_t _imm,
+                ArmISA::IntRegIndex _op1) :
+        ArmISA::PredOp(mnem, _machInst, __opClass),
         dest(_dest), imm(_imm), op1(_op1)
     {}
 
@@ -208,18 +210,19 @@ class RegImmRegOp : public PredOp
             Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
-class RegRegRegImmOp : public PredOp
+class RegRegRegImmOp : public ArmISA::PredOp
 {
   protected:
-    IntRegIndex dest;
-    IntRegIndex op1;
-    IntRegIndex op2;
+    ArmISA::IntRegIndex dest;
+    ArmISA::IntRegIndex op1;
+    ArmISA::IntRegIndex op2;
     uint64_t imm;
 
-    RegRegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
-                   IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
+    RegRegRegImmOp(const char *mnem, ArmISA::ExtMachInst _machInst,
+                   OpClass __opClass, ArmISA::IntRegIndex _dest,
+                   ArmISA::IntRegIndex _op1, ArmISA::IntRegIndex _op2,
                    uint64_t _imm) :
-        PredOp(mnem, _machInst, __opClass),
+        ArmISA::PredOp(mnem, _machInst, __opClass),
         dest(_dest), op1(_op1), op2(_op2), imm(_imm)
     {}
 
@@ -227,18 +230,19 @@ class RegRegRegImmOp : public PredOp
             Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
-class RegRegRegRegOp : public PredOp
+class RegRegRegRegOp : public ArmISA::PredOp
 {
   protected:
-    IntRegIndex dest;
-    IntRegIndex op1;
-    IntRegIndex op2;
-    IntRegIndex op3;
-
-    RegRegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
-                   IntRegIndex _dest, IntRegIndex _op1,
-                   IntRegIndex _op2, IntRegIndex _op3) :
-        PredOp(mnem, _machInst, __opClass),
+    ArmISA::IntRegIndex dest;
+    ArmISA::IntRegIndex op1;
+    ArmISA::IntRegIndex op2;
+    ArmISA::IntRegIndex op3;
+
+    RegRegRegRegOp(const char *mnem, ArmISA::ExtMachInst _machInst,
+                   OpClass __opClass, ArmISA::IntRegIndex _dest,
+                   ArmISA::IntRegIndex _op1, ArmISA::IntRegIndex _op2,
+                   ArmISA::IntRegIndex _op3) :
+        ArmISA::PredOp(mnem, _machInst, __opClass),
         dest(_dest), op1(_op1), op2(_op2), op3(_op3)
     {}
 
@@ -246,16 +250,17 @@ class RegRegRegRegOp : public PredOp
             Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
-class RegRegRegOp : public PredOp
+class RegRegRegOp : public ArmISA::PredOp
 {
   protected:
-    IntRegIndex dest;
-    IntRegIndex op1;
-    IntRegIndex op2;
-
-    RegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
-                IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) :
-        PredOp(mnem, _machInst, __opClass),
+    ArmISA::IntRegIndex dest;
+    ArmISA::IntRegIndex op1;
+    ArmISA::IntRegIndex op2;
+
+    RegRegRegOp(const char *mnem, ArmISA::ExtMachInst _machInst,
+                OpClass __opClass, ArmISA::IntRegIndex _dest,
+                ArmISA::IntRegIndex _op1, ArmISA::IntRegIndex _op2) :
+        ArmISA::PredOp(mnem, _machInst, __opClass),
         dest(_dest), op1(_op1), op2(_op2)
     {}
 
@@ -263,17 +268,17 @@ class RegRegRegOp : public PredOp
             Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
-class RegRegImmOp : public PredOp
+class RegRegImmOp : public ArmISA::PredOp
 {
   protected:
-    IntRegIndex dest;
-    IntRegIndex op1;
+    ArmISA::IntRegIndex dest;
+    ArmISA::IntRegIndex op1;
     uint64_t imm;
 
-    RegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
-                IntRegIndex _dest, IntRegIndex _op1,
-                uint64_t _imm) :
-        PredOp(mnem, _machInst, __opClass),
+    RegRegImmOp(const char *mnem, ArmISA::ExtMachInst _machInst,
+                OpClass __opClass, ArmISA::IntRegIndex _dest,
+                ArmISA::IntRegIndex _op1, uint64_t _imm) :
+        ArmISA::PredOp(mnem, _machInst, __opClass),
         dest(_dest), op1(_op1), imm(_imm)
     {}
 
@@ -281,17 +286,17 @@ class RegRegImmOp : public PredOp
             Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
-class MiscRegRegImmOp : public PredOp
+class MiscRegRegImmOp : public ArmISA::PredOp
 {
   protected:
-    MiscRegIndex dest;
-    IntRegIndex op1;
+    ArmISA::MiscRegIndex dest;
+    ArmISA::IntRegIndex op1;
     uint64_t imm;
 
-    MiscRegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
-                    MiscRegIndex _dest, IntRegIndex _op1,
-                    uint64_t _imm) :
-        PredOp(mnem, _machInst, __opClass),
+    MiscRegRegImmOp(const char *mnem, ArmISA::ExtMachInst _machInst,
+                    OpClass __opClass, ArmISA::MiscRegIndex _dest,
+                    ArmISA::IntRegIndex _op1, uint64_t _imm) :
+        ArmISA::PredOp(mnem, _machInst, __opClass),
         dest(_dest), op1(_op1), imm(_imm)
     {}
 
@@ -299,17 +304,17 @@ class MiscRegRegImmOp : public PredOp
             Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
-class RegMiscRegImmOp : public PredOp
+class RegMiscRegImmOp : public ArmISA::PredOp
 {
   protected:
-    IntRegIndex dest;
-    MiscRegIndex op1;
+    ArmISA::IntRegIndex dest;
+    ArmISA::MiscRegIndex op1;
     uint64_t imm;
 
-    RegMiscRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
-                    IntRegIndex _dest, MiscRegIndex _op1,
-                    uint64_t _imm) :
-        PredOp(mnem, _machInst, __opClass),
+    RegMiscRegImmOp(const char *mnem, ArmISA::ExtMachInst _machInst,
+                    OpClass __opClass, ArmISA::IntRegIndex _dest,
+                    ArmISA::MiscRegIndex _op1, uint64_t _imm) :
+        ArmISA::PredOp(mnem, _machInst, __opClass),
         dest(_dest), op1(_op1), imm(_imm)
     {}
 
@@ -317,16 +322,17 @@ class RegMiscRegImmOp : public PredOp
             Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
-class RegImmImmOp : public PredOp
+class RegImmImmOp : public ArmISA::PredOp
 {
   protected:
-    IntRegIndex dest;
+    ArmISA::IntRegIndex dest;
     uint64_t imm1;
     uint64_t imm2;
 
-    RegImmImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
-                IntRegIndex _dest, uint64_t _imm1, uint64_t _imm2) :
-        PredOp(mnem, _machInst, __opClass),
+    RegImmImmOp(const char *mnem, ArmISA::ExtMachInst _machInst,
+                OpClass __opClass, ArmISA::IntRegIndex _dest,
+                uint64_t _imm1, uint64_t _imm2) :
+        ArmISA::PredOp(mnem, _machInst, __opClass),
         dest(_dest), imm1(_imm1), imm2(_imm2)
     {}
 
@@ -334,18 +340,18 @@ class RegImmImmOp : public PredOp
             Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
-class RegRegImmImmOp : public PredOp
+class RegRegImmImmOp : public ArmISA::PredOp
 {
   protected:
-    IntRegIndex dest;
-    IntRegIndex op1;
+    ArmISA::IntRegIndex dest;
+    ArmISA::IntRegIndex op1;
     uint64_t imm1;
     uint64_t imm2;
 
-    RegRegImmImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
-                   IntRegIndex _dest, IntRegIndex _op1,
-                   uint64_t _imm1, uint64_t _imm2) :
-        PredOp(mnem, _machInst, __opClass),
+    RegRegImmImmOp(const char *mnem, ArmISA::ExtMachInst _machInst,
+                   OpClass __opClass, ArmISA::IntRegIndex _dest,
+                   ArmISA::IntRegIndex _op1, uint64_t _imm1, uint64_t _imm2) :
+        ArmISA::PredOp(mnem, _machInst, __opClass),
         dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2)
     {}
 
@@ -353,19 +359,20 @@ class RegRegImmImmOp : public PredOp
             Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
-class RegImmRegShiftOp : public PredOp
+class RegImmRegShiftOp : public ArmISA::PredOp
 {
   protected:
-    IntRegIndex dest;
+    ArmISA::IntRegIndex dest;
     uint64_t imm;
-    IntRegIndex op1;
+    ArmISA::IntRegIndex op1;
     int32_t shiftAmt;
-    ArmShiftType shiftType;
+    ArmISA::ArmShiftType shiftType;
 
-    RegImmRegShiftOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
-                     IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1,
-                     int32_t _shiftAmt, ArmShiftType _shiftType) :
-        PredOp(mnem, _machInst, __opClass),
+    RegImmRegShiftOp(const char *mnem, ArmISA::ExtMachInst _machInst,
+                     OpClass __opClass, ArmISA::IntRegIndex _dest,
+                     uint64_t _imm, ArmISA::IntRegIndex _op1,
+                     int32_t _shiftAmt, ArmISA::ArmShiftType _shiftType) :
+        ArmISA::PredOp(mnem, _machInst, __opClass),
         dest(_dest), imm(_imm), op1(_op1),
         shiftAmt(_shiftAmt), shiftType(_shiftType)
     {}
@@ -374,12 +381,13 @@ class RegImmRegShiftOp : public PredOp
             Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
-class UnknownOp : public PredOp
+class UnknownOp : public ArmISA::PredOp
 {
   protected:
 
-    UnknownOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
-        PredOp(mnem, _machInst, __opClass)
+    UnknownOp(const char *mnem, ArmISA::ExtMachInst _machInst,
+              OpClass __opClass) :
+        ArmISA::PredOp(mnem, _machInst, __opClass)
     {}
 
     std::string generateDisassembly(
@@ -392,15 +400,15 @@ class UnknownOp : public PredOp
  * we can still check for hyp traps, as the normal nop instruction
  * does not.
  */
-class McrMrcMiscInst : public ArmStaticInst
+class McrMrcMiscInst : public ArmISA::ArmStaticInst
 {
   protected:
     uint64_t iss;
-    MiscRegIndex miscReg;
+    ArmISA::MiscRegIndex miscReg;
 
   public:
-    McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst,
-                   uint64_t _iss, MiscRegIndex _miscReg);
+    McrMrcMiscInst(const char *_mnemonic, ArmISA::ExtMachInst _machInst,
+                   uint64_t _iss, ArmISA::MiscRegIndex _miscReg);
 
     Fault execute(ExecContext *xc,
                   Trace::InstRecord *traceData) const override;
@@ -417,8 +425,8 @@ class McrMrcMiscInst : public ArmStaticInst
 class McrMrcImplDefined : public McrMrcMiscInst
 {
   public:
-    McrMrcImplDefined(const char *_mnemonic, ExtMachInst _machInst,
-                      uint64_t _iss, MiscRegIndex _miscReg);
+    McrMrcImplDefined(const char *_mnemonic, ArmISA::ExtMachInst _machInst,
+                      uint64_t _iss, ArmISA::MiscRegIndex _miscReg);
 
     Fault execute(ExecContext *xc,
                   Trace::InstRecord *traceData) const override;
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 3b3ef5d57..47a8ad95a 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -38,6 +38,8 @@
 #include "arch/arm/insts/misc64.hh"
 #include "arch/arm/isa.hh"
 
+using namespace ArmISA;
+
 std::string
 ImmOp64::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 {
diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index 47d5d329f..7aedd5558 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -40,32 +40,33 @@
 
 #include "arch/arm/insts/static_inst.hh"
 
-class ImmOp64 : public ArmStaticInst
+class ImmOp64 : public ArmISA::ArmStaticInst
 {
   protected:
     uint64_t imm;
 
-    ImmOp64(const char *mnem, ExtMachInst _machInst,
+    ImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
             OpClass __opClass, uint64_t _imm) :
-        ArmStaticInst(mnem, _machInst, __opClass), imm(_imm)
+        ArmISA::ArmStaticInst(mnem, _machInst, __opClass), imm(_imm)
     {}
 
     std::string generateDisassembly(
             Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
-class RegRegImmImmOp64 : public ArmStaticInst
+class RegRegImmImmOp64 : public ArmISA::ArmStaticInst
 {
   protected:
-    IntRegIndex dest;
-    IntRegIndex op1;
+    ArmISA::IntRegIndex dest;
+    ArmISA::IntRegIndex op1;
     uint64_t imm1;
     uint64_t imm2;
 
-    RegRegImmImmOp64(const char *mnem, ExtMachInst _machInst,
-                     OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
-                     uint64_t _imm1, uint64_t _imm2) :
-        ArmStaticInst(mnem, _machInst, __opClass),
+    RegRegImmImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
+                     OpClass __opClass, ArmISA::IntRegIndex _dest,
+                     ArmISA::IntRegIndex _op1, uint64_t _imm1,
+                     int64_t _imm2) :
+        ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
         dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2)
     {}
 
@@ -73,18 +74,19 @@ class RegRegImmImmOp64 : public ArmStaticInst
             Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
-class RegRegRegImmOp64 : public ArmStaticInst
+class RegRegRegImmOp64 : public ArmISA::ArmStaticInst
 {
   protected:
-    IntRegIndex dest;
-    IntRegIndex op1;
-    IntRegIndex op2;
+    ArmISA::IntRegIndex dest;
+    ArmISA::IntRegIndex op1;
+    ArmISA::IntRegIndex op2;
     uint64_t imm;
 
-    RegRegRegImmOp64(const char *mnem, ExtMachInst _machInst,
-                     OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
-                     IntRegIndex _op2, uint64_t _imm) :
-        ArmStaticInst(mnem, _machInst, __opClass),
+    RegRegRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
+                     OpClass __opClass, ArmISA::IntRegIndex _dest,
+                     ArmISA::IntRegIndex _op1, ArmISA::IntRegIndex _op2,
+                     uint64_t _imm) :
+        ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
         dest(_dest), op1(_op1), op2(_op2), imm(_imm)
     {}
 
@@ -92,12 +94,13 @@ class RegRegRegImmOp64 : public ArmStaticInst
             Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
-class UnknownOp64 : public ArmStaticInst
+class UnknownOp64 : public ArmISA::ArmStaticInst
 {
   protected:
 
-    UnknownOp64(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
-        ArmStaticInst(mnem, _machInst, __opClass)
+    UnknownOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
+            OpClass __opClass) :
+        ArmISA::ArmStaticInst(mnem, _machInst, __opClass)
     {}
 
     std::string generateDisassembly(
@@ -115,30 +118,30 @@ class UnknownOp64 : public ArmStaticInst
  * functionalities even if there is no data movement between GPRs and
  * system register.
  */
-class MiscRegOp64 : public ArmStaticInst
+class MiscRegOp64 : public ArmISA::ArmStaticInst
 {
   protected:
     bool miscRead;
 
-    MiscRegOp64(const char *mnem, ExtMachInst _machInst,
+    MiscRegOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
                 OpClass __opClass, bool misc_read) :
-        ArmStaticInst(mnem, _machInst, __opClass),
+        ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
         miscRead(misc_read)
     {}
 
-    Fault trap(ThreadContext *tc, MiscRegIndex misc_reg,
-               ExceptionLevel el, uint32_t immediate) const;
+    Fault trap(ThreadContext *tc, ArmISA::MiscRegIndex misc_reg,
+               ArmISA::ExceptionLevel el, uint32_t immediate) const;
   private:
-    bool checkEL1Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
-                      ExceptionLevel el, ExceptionClass &ec,
+    bool checkEL1Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg,
+                      ArmISA::ExceptionLevel el, ArmISA::ExceptionClass &ec,
                       uint32_t &immediate) const;
 
-    bool checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
-                      ExceptionLevel el, ExceptionClass &ec,
+    bool checkEL2Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg,
+                      ArmISA::ExceptionLevel el, ArmISA::ExceptionClass &ec,
                       uint32_t &immediate) const;
 
-    bool checkEL3Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
-                      ExceptionLevel el, ExceptionClass &ec,
+    bool checkEL3Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg,
+                      ArmISA::ExceptionLevel el, ArmISA::ExceptionClass &ec,
                       uint32_t &immediate) const;
 
 };
@@ -146,11 +149,11 @@ class MiscRegOp64 : public ArmStaticInst
 class MiscRegImmOp64 : public MiscRegOp64
 {
   protected:
-    MiscRegIndex dest;
+    ArmISA::MiscRegIndex dest;
     uint32_t imm;
 
-    MiscRegImmOp64(const char *mnem, ExtMachInst _machInst,
-                   OpClass __opClass, MiscRegIndex _dest,
+    MiscRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
+                   OpClass __opClass, ArmISA::MiscRegIndex _dest,
                    uint32_t _imm) :
         MiscRegOp64(mnem, _machInst, __opClass, false),
         dest(_dest), imm(_imm)
@@ -170,13 +173,13 @@ class MiscRegImmOp64 : public MiscRegOp64
 class MiscRegRegImmOp64 : public MiscRegOp64
 {
   protected:
-    MiscRegIndex dest;
-    IntRegIndex op1;
+    ArmISA::MiscRegIndex dest;
+    ArmISA::IntRegIndex op1;
     uint32_t imm;
 
-    MiscRegRegImmOp64(const char *mnem, ExtMachInst _machInst,
-                      OpClass __opClass, MiscRegIndex _dest,
-                      IntRegIndex _op1, uint32_t _imm) :
+    MiscRegRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
+                      OpClass __opClass, ArmISA::MiscRegIndex _dest,
+                      ArmISA::IntRegIndex _op1, uint32_t _imm) :
         MiscRegOp64(mnem, _machInst, __opClass, false),
         dest(_dest), op1(_op1), imm(_imm)
     {}
@@ -188,13 +191,13 @@ class MiscRegRegImmOp64 : public MiscRegOp64
 class RegMiscRegImmOp64 : public MiscRegOp64
 {
   protected:
-    IntRegIndex dest;
-    MiscRegIndex op1;
+    ArmISA::IntRegIndex dest;
+    ArmISA::MiscRegIndex op1;
     uint32_t imm;
 
-    RegMiscRegImmOp64(const char *mnem, ExtMachInst _machInst,
-                      OpClass __opClass, IntRegIndex _dest,
-                      MiscRegIndex _op1, uint32_t _imm) :
+    RegMiscRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
+                      OpClass __opClass, ArmISA::IntRegIndex _dest,
+                      ArmISA::MiscRegIndex _op1, uint32_t _imm) :
         MiscRegOp64(mnem, _machInst, __opClass, true),
         dest(_dest), op1(_op1), imm(_imm)
     {}
@@ -207,20 +210,20 @@ class MiscRegImplDefined64 : public MiscRegOp64
 {
   protected:
     const std::string fullMnemonic;
-    const MiscRegIndex miscReg;
+    const ArmISA::MiscRegIndex miscReg;
     const uint32_t imm;
     const bool warning;
 
   public:
-    MiscRegImplDefined64(const char *mnem, ExtMachInst _machInst,
-                         MiscRegIndex misc_reg, bool misc_read,
+    MiscRegImplDefined64(const char *mnem, ArmISA::ExtMachInst _machInst,
+                         ArmISA::MiscRegIndex misc_reg, bool misc_read,
                          uint32_t _imm, const std::string full_mnem,
                          bool _warning) :
         MiscRegOp64(mnem, _machInst, No_OpClass, misc_read),
         fullMnemonic(full_mnem), miscReg(misc_reg), imm(_imm),
         warning(_warning)
     {
-        assert(miscReg == MISCREG_IMPDEF_UNIMPL);
+        assert(miscReg == ArmISA::MISCREG_IMPDEF_UNIMPL);
     }
 
   protected:
diff --git a/src/arch/arm/insts/pseudo.cc b/src/arch/arm/insts/pseudo.cc
index bf1fecc37..ff73dbd09 100644
--- a/src/arch/arm/insts/pseudo.cc
+++ b/src/arch/arm/insts/pseudo.cc
@@ -42,6 +42,8 @@
 
 #include "cpu/exec_context.hh"
 
+using namespace ArmISA;
+
 DecoderFaultInst::DecoderFaultInst(ExtMachInst _machInst)
     : ArmStaticInst("gem5decoderFault", _machInst, No_OpClass),
       faultId(static_cast<DecoderFault>(
diff --git a/src/arch/arm/insts/pseudo.hh b/src/arch/arm/insts/pseudo.hh
index 30a98264e..964faf736 100644
--- a/src/arch/arm/insts/pseudo.hh
+++ b/src/arch/arm/insts/pseudo.hh
@@ -43,15 +43,15 @@
 
 #include "arch/arm/insts/static_inst.hh"
 
-class DecoderFaultInst : public ArmStaticInst
+class DecoderFaultInst : public ArmISA::ArmStaticInst
 {
   protected:
-    DecoderFault faultId;
+    ArmISA::DecoderFault faultId;
 
     const char *faultName() const;
 
   public:
-    DecoderFaultInst(ExtMachInst _machInst);
+    DecoderFaultInst(ArmISA::ExtMachInst _machInst);
 
     Fault execute(ExecContext *xc,
                   Trace::InstRecord *traceData) const override;
@@ -67,7 +67,7 @@ class DecoderFaultInst : public ArmStaticInst
  * 'Unknown' class is used for unrecognized/illegal instructions.
  * This is a leaf class.
  */
-class FailUnimplemented : public ArmStaticInst
+class FailUnimplemented : public ArmISA::ArmStaticInst
 {
   private:
     /// Full mnemonic for MRC and MCR instructions including the
@@ -75,8 +75,8 @@ class FailUnimplemented : public ArmStaticInst
     std::string fullMnemonic;
 
   public:
-    FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst);
-    FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst,
+    FailUnimplemented(const char *_mnemonic, ArmISA::ExtMachInst _machInst);
+    FailUnimplemented(const char *_mnemonic, ArmISA::ExtMachInst _machInst,
                       const std::string& _fullMnemonic);
 
     Fault execute(ExecContext *xc,
@@ -95,7 +95,7 @@ class FailUnimplemented : public ArmStaticInst
  * probably make the 'warned' flag a static member of the derived
  * class.
  */
-class WarnUnimplemented : public ArmStaticInst
+class WarnUnimplemented : public ArmISA::ArmStaticInst
 {
   private:
     /// Have we warned on this instruction yet?
@@ -105,8 +105,8 @@ class WarnUnimplemented : public ArmStaticInst
     std::string fullMnemonic;
 
   public:
-    WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst);
-    WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst,
+    WarnUnimplemented(const char *_mnemonic, ArmISA::ExtMachInst _machInst);
+    WarnUnimplemented(const char *_mnemonic, ArmISA::ExtMachInst _machInst,
                       const std::string& _fullMnemonic);
 
     Fault execute(ExecContext *xc,
@@ -123,19 +123,19 @@ class WarnUnimplemented : public ArmStaticInst
  * The sole purpose of this instruction is to generate an appropriate
  * fault when executed.
  */
-class IllegalExecInst : public ArmStaticInst
+class IllegalExecInst : public ArmISA::ArmStaticInst
 {
   public:
-    IllegalExecInst(ExtMachInst _machInst);
+    IllegalExecInst(ArmISA::ExtMachInst _machInst);
 
     Fault execute(ExecContext *xc,
                   Trace::InstRecord *traceData) const override;
 };
 
-class DebugStep : public ArmStaticInst
+class DebugStep : public ArmISA::ArmStaticInst
 {
   public:
-    DebugStep(ExtMachInst _machInst);
+    DebugStep(ArmISA::ExtMachInst _machInst);
 
     Fault execute(ExecContext *xc,
                   Trace::InstRecord *traceData) const override;
diff --git a/src/arch/arm/insts/vfp.cc b/src/arch/arm/insts/vfp.cc
index 85ca1bcec..a84b7138b 100644
--- a/src/arch/arm/insts/vfp.cc
+++ b/src/arch/arm/insts/vfp.cc
@@ -37,6 +37,8 @@
 
 #include "arch/arm/insts/vfp.hh"
 
+using namespace ArmISA;
+
 /*
  * The asm statements below are to keep gcc from reordering code. Otherwise
  * the rounding mode might be set after the operation it was intended for, the
diff --git a/src/arch/arm/isa/includes.isa b/src/arch/arm/isa/includes.isa
index 11de6d88f..13b47c8e0 100644
--- a/src/arch/arm/isa/includes.isa
+++ b/src/arch/arm/isa/includes.isa
@@ -71,6 +71,11 @@ output header {{
 #include "mem/packet.hh"
 #include "sim/faults.hh"
 
+namespace ArmISAInst
+{
+using namespace ArmISA;
+}
+
 }};
 
 output decoder {{
diff --git a/src/arch/arm/isa/insts/amo64.isa b/src/arch/arm/isa/insts/amo64.isa
index 6d3a5151e..1fe9b7a1e 100644
--- a/src/arch/arm/isa/insts/amo64.isa
+++ b/src/arch/arm/isa/insts/amo64.isa
@@ -124,11 +124,11 @@ let {{
 
 
             fa_code = '''
-               fault->annotate(ArmFault::SAS, %s);
-               fault->annotate(ArmFault::SSE, %s);
-               fault->annotate(ArmFault::SRT, dest);
-               fault->annotate(ArmFault::SF, %s);
-               fault->annotate(ArmFault::AR, %s);
+               fault->annotate(ArmISA::ArmFault::SAS, %s);
+               fault->annotate(ArmISA::ArmFault::SSE, %s);
+               fault->annotate(ArmISA::ArmFault::SRT, dest);
+               fault->annotate(ArmISA::ArmFault::SF, %s);
+               fault->annotate(ArmISA::ArmFault::AR, %s);
                ''' % (sas_code,
                      "true" if not self.unsign else "false",
                      "true" if self.size == 8 else "false",
diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa
index 1b099bf91..d5a5869fb 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -403,8 +403,8 @@ let {{
     # The DC ZVA instruction is not classified as a cache maintenance
     # instruction, and therefore we shouldn't annotate it.
     cachem_fa = '''
-        fault->annotate(ArmFault::CM, 1);
-        fault->annotate(ArmFault::OFA, faultAddr);
+        fault->annotate(ArmISA::ArmFault::CM, 1);
+        fault->annotate(ArmISA::ArmFault::OFA, faultAddr);
     '''
 
     msrdccvau_ea_code = msr_check_code
diff --git a/src/arch/arm/isa/insts/ldr64.isa b/src/arch/arm/isa/insts/ldr64.isa
index 2cbc8b640..51f53897b 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -153,11 +153,11 @@ let {{
             fa_code = None
             if not self.micro and self.flavor in ("normal", "widen", "acquire"):
                 fa_code = '''
-                    fault->annotate(ArmFault::SAS, %s);
-                    fault->annotate(ArmFault::SSE, %s);
-                    fault->annotate(ArmFault::SRT, dest);
-                    fault->annotate(ArmFault::SF, %s);
-                    fault->annotate(ArmFault::AR, %s);
+                    fault->annotate(ArmISA::ArmFault::SAS, %s);
+                    fault->annotate(ArmISA::ArmFault::SSE, %s);
+                    fault->annotate(ArmISA::ArmFault::SRT, dest);
+                    fault->annotate(ArmISA::ArmFault::SF, %s);
+                    fault->annotate(ArmISA::ArmFault::AR, %s);
                 ''' % ("0" if self.size == 1 else
                        "1" if self.size == 2 else
                        "2" if self.size == 4 else "3",
diff --git a/src/arch/arm/isa/insts/mem.isa b/src/arch/arm/isa/insts/mem.isa
index 0605d7bbf..685f764a6 100644
--- a/src/arch/arm/isa/insts/mem.isa
+++ b/src/arch/arm/isa/insts/mem.isa
@@ -67,9 +67,9 @@ let {{
             elif wbDecl == None:
                 codeBlobs["fa_code"] = '''
                     if (dest != INTREG_PC) {
-                        fault->annotate(ArmFault::SAS, %s);
-                        fault->annotate(ArmFault::SSE, %s);
-                        fault->annotate(ArmFault::SRT, dest);
+                        fault->annotate(ArmISA::ArmFault::SAS, %s);
+                        fault->annotate(ArmISA::ArmFault::SSE, %s);
+                        fault->annotate(ArmISA::ArmFault::SRT, dest);
                     }
                 ''' %("0"    if size == 1 else
                       "1"    if size == 2 else "2",
diff --git a/src/arch/arm/isa/insts/str64.isa b/src/arch/arm/isa/insts/str64.isa
index ebdad361f..ac845336a 100644
--- a/src/arch/arm/isa/insts/str64.isa
+++ b/src/arch/arm/isa/insts/str64.isa
@@ -99,11 +99,11 @@ let {{
             fa_code = None
             if not self.micro and self.flavor in ("normal", "release"):
                 fa_code = '''
-                    fault->annotate(ArmFault::SAS, %s);
-                    fault->annotate(ArmFault::SSE, false);
-                    fault->annotate(ArmFault::SRT, dest);
-                    fault->annotate(ArmFault::SF, %s);
-                    fault->annotate(ArmFault::AR, %s);
+                    fault->annotate(ArmISA::ArmFault::SAS, %s);
+                    fault->annotate(ArmISA::ArmFault::SSE, false);
+                    fault->annotate(ArmISA::ArmFault::SRT, dest);
+                    fault->annotate(ArmISA::ArmFault::SF, %s);
+                    fault->annotate(ArmISA::ArmFault::AR, %s);
                 ''' % ("0" if self.size == 1 else
                        "1" if self.size == 2 else
                        "2" if self.size == 4 else "3",
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index c9043de50..1496facb5 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -684,7 +684,7 @@ def template LoadStoreImmDeclare {{
                           Trace::InstRecord *) const override;
 
         void
-        annotateFault(ArmFault *fault) override
+        annotateFault(ArmISA::ArmFault *fault) override
         {
             %(fa_code)s
         }
@@ -753,7 +753,7 @@ def template StoreRegDeclare {{
                           Trace::InstRecord *) const override;
 
         void
-        annotateFault(ArmFault *fault) override
+        annotateFault(ArmISA::ArmFault *fault) override
         {
             %(fa_code)s
         }
@@ -802,7 +802,7 @@ def template LoadRegDeclare {{
                           Trace::InstRecord *) const override;
 
         void
-        annotateFault(ArmFault *fault) override
+        annotateFault(ArmISA::ArmFault *fault) override
         {
             %(fa_code)s
         }
@@ -827,7 +827,7 @@ def template LoadImmDeclare {{
                           Trace::InstRecord *) const override;
 
         void
-        annotateFault(ArmFault *fault) override
+        annotateFault(ArmISA::ArmFault *fault) override
         {
             %(fa_code)s
         }
diff --git a/src/arch/arm/isa/templates/mem64.isa b/src/arch/arm/isa/templates/mem64.isa
index 0baed2c67..ed43cd77a 100644
--- a/src/arch/arm/isa/templates/mem64.isa
+++ b/src/arch/arm/isa/templates/mem64.isa
@@ -287,7 +287,7 @@ def template DCStore64Declare {{
                           Trace::InstRecord *) const override;
 
         void
-        annotateFault(ArmFault *fault) override
+        annotateFault(ArmISA::ArmFault *fault) override
         {
             %(fa_code)s
         }
@@ -372,7 +372,7 @@ def template LoadStoreImm64Declare {{
                           Trace::InstRecord *) const override;
 
         void
-        annotateFault(ArmFault *fault) override
+        annotateFault(ArmISA::ArmFault *fault) override
         {
             %(fa_code)s
         }
@@ -396,7 +396,7 @@ def template LoadStoreImmU64Declare {{
                           Trace::InstRecord *) const override;
 
         void
-        annotateFault(ArmFault *fault) override
+        annotateFault(ArmISA::ArmFault *fault) override
         {
             %(fa_code)s
         }
@@ -420,7 +420,7 @@ def template LoadStoreImmDU64Declare {{
                           Trace::InstRecord *) const override;
 
         void
-        annotateFault(ArmFault *fault) override
+        annotateFault(ArmISA::ArmFault *fault) override
         {
             %(fa_code)s
         }
@@ -464,7 +464,7 @@ def template LoadStoreReg64Declare {{
                           Trace::InstRecord *) const override;
 
         void
-        annotateFault(ArmFault *fault) override
+        annotateFault(ArmISA::ArmFault *fault) override
         {
             %(fa_code)s
         }
@@ -489,7 +489,7 @@ def template LoadStoreRegU64Declare {{
                           Trace::InstRecord *) const override;
 
         void
-        annotateFault(ArmFault *fault) override
+        annotateFault(ArmISA::ArmFault *fault) override
         {
             %(fa_code)s
         }
@@ -511,7 +511,7 @@ def template LoadStoreRaw64Declare {{
                           Trace::InstRecord *) const override;
 
         void
-        annotateFault(ArmFault *fault) override
+        annotateFault(ArmISA::ArmFault *fault) override
         {
             %(fa_code)s
         }
@@ -533,7 +533,7 @@ def template LoadStoreEx64Declare {{
                           Trace::InstRecord *) const override;
 
         void
-        annotateFault(ArmFault *fault) override
+        annotateFault(ArmISA::ArmFault *fault) override
         {
             %(fa_code)s
         }
@@ -554,7 +554,7 @@ def template LoadStoreLit64Declare {{
                           Trace::InstRecord *) const override;
 
         void
-        annotateFault(ArmFault *fault) override
+        annotateFault(ArmISA::ArmFault *fault) override
         {
             %(fa_code)s
         }
@@ -577,7 +577,7 @@ def template LoadStoreLitU64Declare {{
                           Trace::InstRecord *) const override;
 
         void
-        annotateFault(ArmFault *fault) override
+        annotateFault(ArmISA::ArmFault *fault) override
         {
             %(fa_code)s
         }
@@ -814,7 +814,7 @@ def template AmoOpDeclare {{
                           Trace::InstRecord *) const override;
 
         void
-        annotateFault(ArmFault *fault) override
+        annotateFault(ArmISA::ArmFault *fault) override
         {
             %(fa_code)s
         }
@@ -851,7 +851,7 @@ def template AmoPairOpDeclare {{
                           Trace::InstRecord *) const override;
 
         void
-        annotateFault(ArmFault *fault) override
+        annotateFault(ArmISA::ArmFault *fault) override
         {
             %(fa_code)s
         }
@@ -896,7 +896,7 @@ def template AmoArithmeticOpDeclare {{
                           Trace::InstRecord *) const override;
 
         void
-        annotateFault(ArmFault *fault) override
+        annotateFault(ArmISA::ArmFault *fault) override
         {
             %(fa_code)s
         }
diff --git a/src/arch/arm/isa/templates/sve_mem.isa b/src/arch/arm/isa/templates/sve_mem.isa
index e1f725c71..46d38c460 100644
--- a/src/arch/arm/isa/templates/sve_mem.isa
+++ b/src/arch/arm/isa/templates/sve_mem.isa
@@ -56,7 +56,7 @@ def template SveMemFillSpillOpDeclare {{
                           Trace::InstRecord *) const override;
 
         void
-        annotateFault(ArmFault *fault) override
+        annotateFault(ArmISA::ArmFault *fault) override
         {
             %(fa_code)s
         }
@@ -86,7 +86,7 @@ def template SveContigMemSSOpDeclare {{
                           Trace::InstRecord *) const override;
 
         virtual void
-        annotateFault(ArmFault *fault) override {
+        annotateFault(ArmISA::ArmFault *fault) override {
             %(fa_code)s
         }
     };
@@ -115,7 +115,7 @@ def template SveContigMemSIOpDeclare {{
                           Trace::InstRecord *) const override;
 
         virtual void
-        annotateFault(ArmFault *fault) override {
+        annotateFault(ArmISA::ArmFault *fault) override {
             %(fa_code)s
         }
     };
@@ -430,7 +430,7 @@ def template SveIndexedMemVIMicroopDeclare {{
                           Trace::InstRecord *) const override;
 
         virtual void
-        annotateFault(ArmFault *fault) override
+        annotateFault(ArmISA::ArmFault *fault) override
         {
             %(fa_code)s
         }
@@ -511,7 +511,7 @@ def template SveIndexedMemSVMicroopDeclare {{
                           Trace::InstRecord *) const override;
 
         virtual void
-        annotateFault(ArmFault *fault) override
+        annotateFault(ArmISA::ArmFault *fault) override
         {
             %(fa_code)s
         }
@@ -867,7 +867,7 @@ def template SveStructMemSIMicroopDeclare {{
                           Trace::InstRecord *) const override;
 
         virtual void
-        annotateFault(ArmFault *fault) override
+        annotateFault(ArmISA::ArmFault *fault) override
         {
             %(fa_code)s
         }
@@ -1132,7 +1132,7 @@ def template SveStructMemSSMicroopDeclare {{
                           Trace::InstRecord *) const override;
 
         virtual void
-        annotateFault(ArmFault *fault) override
+        annotateFault(ArmISA::ArmFault *fault) override
         {
             %(fa_code)s
         }
diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index 81d4b4f94..798db72fa 100644
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -52,6 +52,4 @@ namespace ArmISA
     const Addr PageBytes = ULL(1) << PageShift;
 } // namespace ArmISA
 
-using namespace ArmISA;
-
 #endif // __ARCH_ARM_ISA_TRAITS_HH__
diff --git a/src/arch/arm/linux/fs_workload.cc b/src/arch/arm/linux/fs_workload.cc
index ac308f50f..8aba285cb 100644
--- a/src/arch/arm/linux/fs_workload.cc
+++ b/src/arch/arm/linux/fs_workload.cc
@@ -359,8 +359,8 @@ DumpStats::process(ThreadContext *tc)
 
 } // namespace ArmISA
 
-FsLinux *
+ArmISA::FsLinux *
 ArmFsLinuxParams::create()
 {
-    return new FsLinux(this);
+    return new ArmISA::FsLinux(this);
 }
diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc
index 0a0a250c6..e40b74c8d 100644
--- a/src/arch/arm/nativetrace.cc
+++ b/src/arch/arm/nativetrace.cc
@@ -47,6 +47,8 @@
 #include "params/ArmNativeTrace.hh"
 #include "sim/byteswap.hh"
 
+using namespace ArmISA;
+
 namespace Trace {
 
 #if TRACING_ON
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 9145b95cc..7009b31dd 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -53,6 +53,7 @@
 
 using namespace std;
 using namespace Linux;
+using namespace ArmISA;
 
 ArmSystem::ArmSystem(Params *p)
     : System(p),
diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index 6422e5a5b..62dfe76e6 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -204,14 +204,14 @@ class ArmSystem : public System
     bool highestELIs64() const { return _highestELIs64; }
 
     /** Returns the highest implemented exception level */
-    ExceptionLevel
+    ArmISA::ExceptionLevel
     highestEL() const
     {
         if (_haveSecurity)
-            return EL3;
+            return ArmISA::EL3;
         if (_haveVirtualization)
-            return EL2;
-        return EL1;
+            return ArmISA::EL2;
+        return ArmISA::EL1;
     }
 
     /** Returns the reset address if the highest implemented exception level is
@@ -297,10 +297,10 @@ class ArmSystem : public System
     /** Returns the highest implemented exception level for the system of a
      * specific thread context
      */
-    static ExceptionLevel highestEL(ThreadContext *tc);
+    static ArmISA::ExceptionLevel highestEL(ThreadContext *tc);
 
     /** Return true if the system implements a specific exception level */
-    static bool haveEL(ThreadContext *tc, ExceptionLevel el);
+    static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el);
 
     /** Returns true if the system of a specific thread context implements the
      * transactional memory extension (TME)
diff --git a/src/arch/arm/tracers/tarmac_record.cc b/src/arch/arm/tracers/tarmac_record.cc
index 4b7f43d23..3969b6d5d 100644
--- a/src/arch/arm/tracers/tarmac_record.cc
+++ b/src/arch/arm/tracers/tarmac_record.cc
@@ -40,6 +40,8 @@
 #include "arch/arm/insts/static_inst.hh"
 #include "tarmac_tracer.hh"
 
+using namespace ArmISA;
+
 namespace Trace {
 
 // TARMAC Instruction Record static variables
diff --git a/src/arch/arm/tracers/tarmac_record_v8.cc b/src/arch/arm/tracers/tarmac_record_v8.cc
index 18fe74c9b..fa4304f33 100644
--- a/src/arch/arm/tracers/tarmac_record_v8.cc
+++ b/src/arch/arm/tracers/tarmac_record_v8.cc
@@ -41,6 +41,8 @@
 #include "arch/arm/tlb.hh"
 #include "arch/arm/tracers/tarmac_tracer.hh"
 
+using namespace ArmISA;
+
 namespace Trace {
 
 TarmacTracerRecordV8::TraceInstEntryV8::TraceInstEntryV8(
diff --git a/src/dev/arm/fvp_base_pwr_ctrl.cc b/src/dev/arm/fvp_base_pwr_ctrl.cc
index 86275989b..fc66e1c33 100644
--- a/src/dev/arm/fvp_base_pwr_ctrl.cc
+++ b/src/dev/arm/fvp_base_pwr_ctrl.cc
@@ -307,7 +307,7 @@ FVPBasePwrCtrl::startCoreUp(ThreadContext *const tc)
     clearWakeRequest(tc);
 
     // InitCPU
-    Reset().invoke(tc);
+    ArmISA::Reset().invoke(tc);
     tc->activate();
 }
 
diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc
index 1b9625752..458a2eb7a 100644
--- a/src/dev/arm/generic_timer.cc
+++ b/src/dev/arm/generic_timer.cc
@@ -50,6 +50,8 @@
 #include "params/GenericTimerMem.hh"
 #include "params/SystemCounter.hh"
 
+using namespace ArmISA;
+
 SystemCounter::SystemCounter(SystemCounterParams *const p)
     : SimObject(p),
       _enabled(true),
diff --git a/src/dev/arm/generic_timer.hh b/src/dev/arm/generic_timer.hh
index 75051c32b..e6308383f 100644
--- a/src/dev/arm/generic_timer.hh
+++ b/src/dev/arm/generic_timer.hh
@@ -302,10 +302,10 @@ class GenericTimer : public SimObject
         uint32_t cntfrq;
 
         /// Kernel control register
-        CNTKCTL cntkctl;
+        ArmISA::CNTKCTL cntkctl;
 
         /// Hypervisor control register
-        CNTHCTL cnthctl;
+        ArmISA::CNTHCTL cnthctl;
 
         /// Thread (HW) context associated to this PE implementation
         ThreadContext *threadContext;
diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc
index 5499e386d..892e7479a 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -47,6 +47,8 @@
 #include "dev/arm/gic_v3_distributor.hh"
 #include "dev/arm/gic_v3_redistributor.hh"
 
+using namespace ArmISA;
+
 const uint8_t Gicv3CPUInterface::GIC_MIN_BPR;
 const uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS;
 
@@ -2039,22 +2041,22 @@ Gicv3CPUInterface::update()
     }
 
     if (hppiCanPreempt()) {
-        ArmISA::InterruptTypes int_type = intSignalType(hppi.group);
+        InterruptTypes int_type = intSignalType(hppi.group);
         DPRINTF(GIC, "Gicv3CPUInterface::update(): "
                 "posting int as %d!\n", int_type);
-        int_type == ArmISA::INT_IRQ ? signal_IRQ = true : signal_FIQ = true;
+        int_type == INT_IRQ ? signal_IRQ = true : signal_FIQ = true;
     }
 
     if (signal_IRQ) {
-        gic->postInt(cpuId, ArmISA::INT_IRQ);
+        gic->postInt(cpuId, INT_IRQ);
     } else {
-        gic->deassertInt(cpuId, ArmISA::INT_IRQ);
+        gic->deassertInt(cpuId, INT_IRQ);
     }
 
     if (signal_FIQ) {
-        gic->postInt(cpuId, ArmISA::INT_FIQ);
+        gic->postInt(cpuId, INT_FIQ);
     } else {
-        gic->deassertInt(cpuId, ArmISA::INT_FIQ);
+        gic->deassertInt(cpuId, INT_FIQ);
     }
 }
 
@@ -2091,18 +2093,18 @@ Gicv3CPUInterface::virtualUpdate()
 
     if (signal_IRQ) {
         DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): "
-                "posting int as %d!\n", ArmISA::INT_VIRT_IRQ);
-        gic->postInt(cpuId, ArmISA::INT_VIRT_IRQ);
+                "posting int as %d!\n", INT_VIRT_IRQ);
+        gic->postInt(cpuId, INT_VIRT_IRQ);
     } else {
-        gic->deassertInt(cpuId, ArmISA::INT_VIRT_IRQ);
+        gic->deassertInt(cpuId, INT_VIRT_IRQ);
     }
 
     if (signal_FIQ) {
         DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): "
-                "posting int as %d!\n", ArmISA::INT_VIRT_FIQ);
-        gic->postInt(cpuId, ArmISA::INT_VIRT_FIQ);
+                "posting int as %d!\n", INT_VIRT_FIQ);
+        gic->postInt(cpuId, INT_VIRT_FIQ);
     } else {
-        gic->deassertInt(cpuId, ArmISA::INT_VIRT_FIQ);
+        gic->deassertInt(cpuId, INT_VIRT_FIQ);
     }
 }
 
@@ -2220,7 +2222,7 @@ Gicv3CPUInterface::virtualIncrementEOICount()
 }
 
 // spec section 4.6.2
-ArmISA::InterruptTypes
+InterruptTypes
 Gicv3CPUInterface::intSignalType(Gicv3::GroupId group) const
 {
     bool is_fiq = false;
@@ -2244,9 +2246,9 @@ Gicv3CPUInterface::intSignalType(Gicv3::GroupId group) const
     }
 
     if (is_fiq) {
-        return ArmISA::INT_FIQ;
+        return INT_FIQ;
     } else {
-        return ArmISA::INT_IRQ;
+        return INT_IRQ;
     }
 }
 
@@ -2334,7 +2336,7 @@ Gicv3CPUInterface::inSecureState() const
 
     CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
     SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR);
-    return ArmISA::inSecureState(scr, cpsr);
+    return ::inSecureState(scr, cpsr);
 }
 
 int
diff --git a/src/dev/arm/gic_v3_cpu_interface.hh b/src/dev/arm/gic_v3_cpu_interface.hh
index d1e38022c..135b53605 100644
--- a/src/dev/arm/gic_v3_cpu_interface.hh
+++ b/src/dev/arm/gic_v3_cpu_interface.hh
@@ -340,8 +340,8 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
     void assertWakeRequest(void);
     void deassertWakeRequest(void);
 
-    RegVal readBankedMiscReg(MiscRegIndex misc_reg) const;
-    void setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const;
+    RegVal readBankedMiscReg(ArmISA::MiscRegIndex misc_reg) const;
+    void setBankedMiscReg(ArmISA::MiscRegIndex misc_reg, RegVal val) const;
   public:
 
     Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id);
diff --git a/src/dev/arm/gic_v3_redistributor.cc b/src/dev/arm/gic_v3_redistributor.cc
index 339039308..4a6fe49db 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -45,6 +45,8 @@
 #include "dev/arm/gic_v3_cpu_interface.hh"
 #include "dev/arm/gic_v3_distributor.hh"
 
+using namespace ArmISA;
+
 const AddrRange Gicv3Redistributor::GICR_IPRIORITYR(SGI_base + 0x0400,
                                                     SGI_base + 0x0420);