From: Clifford Wolf Date: Sun, 27 Jul 2014 11:19:05 +0000 (+0200) Subject: Fixed a bug in opt_clean and some RTLIL API usage cleanups X-Git-Tag: yosys-0.4~393 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dbb3556e3f1e82a6b69d5e8714a0266c1d461c7c;p=yosys.git Fixed a bug in opt_clean and some RTLIL API usage cleanups --- diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index c219bc047..21bda6e4e 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -219,8 +219,8 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool } std::vector maybe_del_wires; - for (auto &it : module->wires_) { - RTLIL::Wire *wire = it.second; + for (auto wire : module->wires()) + { if ((!purge_mode && check_public_name(wire->name)) || wire->port_id != 0 || wire->get_bool_attribute("\\keep")) { RTLIL::SigSpec s1 = RTLIL::SigSpec(wire), s2 = s1; assign_map.apply(s2); @@ -244,6 +244,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool if (!used_signals.check_any(RTLIL::SigSpec(wire))) maybe_del_wires.push_back(wire); } + RTLIL::SigSpec sig = assign_map(RTLIL::SigSpec(wire)); if (!used_signals_nodrivers.check_any(sig)) { std::string unused_bits; @@ -269,7 +270,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool std::set del_wires; int del_wires_count = 0; - for (auto wire : del_wires) + for (auto wire : maybe_del_wires) if (!used_signals.check_any(RTLIL::SigSpec(wire))) { if (check_public_name(wire->name) && verbose) { log(" removing unused non-port wire %s.\n", wire->name.c_str()); diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index bfd0161bf..9a21bdcaf 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -37,20 +37,20 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) SigPool used_signals; SigPool all_signals; - for (auto &it : module->cells_) - for (auto &conn : it.second->connections()) { - if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) + for (auto cell : module->cells()) + for (auto &conn : cell->connections()) { + if (!ct.cell_known(cell->type) || ct.cell_output(cell->type, conn.first)) driven_signals.add(sigmap(conn.second)); - if (!ct.cell_known(it.second->type) || ct.cell_input(it.second->type, conn.first)) + if (!ct.cell_known(cell->type) || ct.cell_input(cell->type, conn.first)) used_signals.add(sigmap(conn.second)); } - for (auto &it : module->wires_) { - if (it.second->port_input) - driven_signals.add(sigmap(it.second)); - if (it.second->port_output) - used_signals.add(sigmap(it.second)); - all_signals.add(sigmap(it.second)); + for (auto wire : module->wires()) { + if (wire->port_input) + driven_signals.add(sigmap(wire)); + if (wire->port_output) + used_signals.add(sigmap(wire)); + all_signals.add(sigmap(wire)); } all_signals.del(driven_signals);