From: Florent Kermarrec Date: Mon, 29 Apr 2019 07:58:51 +0000 (+0200) Subject: cpu: use property methods to return name, endianness, gcc triple/flags, linker output... X-Git-Tag: 24jan2021_ls180~1261 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dbb71af18908d70b83fffdd7a20ef24eefaf520a;p=litex.git cpu: use property methods to return name, endianness, gcc triple/flags, linker output format --- diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py index 4fd6f1e5..70d202ab 100644 --- a/litex/soc/cores/cpu/lm32/core.py +++ b/litex/soc/cores/cpu/lm32/core.py @@ -4,16 +4,39 @@ from migen import * from litex.soc.interconnect import wishbone +CPU_VARIANTS = ["minimal", "lite", "standard"] + class LM32(Module): - name = "lm32" - endianness = "big" - gcc_triple = "lm32-elf" - gcc_flags = "-mbarrel-shift-enabled -mmultiply-enabled -mdivide-enabled -msign-extend-enabled" - linker_output_format = "elf32-lm32" + @property + def name(self): + return "lm32" + + @property + def endianness(self): + return "big" + + @property + def gcc_triple(self): + return "lm32-elf" + + @property + def gcc_flags(self): + flags = "-mbarrel-shift-enabled " + flags += "-mmultiply-enabled " + flags += "-mdivide-enabled " + flags += "-msign-extend-enabled " + flags += "-D__lm32__ " + return flags + + @property + def linker_output_format(self): + return "elf32-lm32" def __init__(self, platform, eba_reset, variant="standard"): - assert variant in ("standard", "lite", "minimal"), "Unsupported variant %s" % variant + assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant + self.platform = platform + self.variant = variant self.reset = Signal() self.ibus = i = wishbone.Interface() self.dbus = d = wishbone.Interface() diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py index 894129b8..3c3c41d6 100644 --- a/litex/soc/cores/cpu/minerva/core.py +++ b/litex/soc/cores/cpu/minerva/core.py @@ -4,16 +4,37 @@ from migen import * from litex.soc.interconnect import wishbone +CPU_VARIANTS = ["standard"] + class Minerva(Module): - name = "minerva" - endianness = "little" - gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf") - gcc_flags = "-march=rv32i -mabi=ilp32" + " -D__minerva__" - linker_output_format = "elf32-littleriscv" + @property + def name(self): + return "minerva" + + @property + def endianness(self): + return "little" + + @property + def gcc_triple(self): + return ("riscv64-unknown-elf", "riscv32-unknown-elf") + + @property + def gcc_flags(self): + flags = "-march=rv32i " + flags += "-mabi=ilp32 " + flags += "-D__minerva__ " + return flags + + @property + def linker_output_format(self): + return "elf32-littleriscv" def __init__(self, platform, cpu_reset_address, variant="standard"): assert variant is "standard", "Unsupported variant %s" % variant + self.platform = platform + self.variant = variant self.reset = Signal() self.ibus = wishbone.Interface() self.dbus = wishbone.Interface() diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py index f6611c3e..bb46a6a6 100644 --- a/litex/soc/cores/cpu/mor1kx/core.py +++ b/litex/soc/cores/cpu/mor1kx/core.py @@ -5,16 +5,52 @@ from migen import * from litex.soc.interconnect import wishbone +CPU_VARIANTS = ["standard", "linux"] + class MOR1KX(Module): - name = "or1k" - endianness = "big" - gcc_triple = "or1k-elf" - gcc_flags = "-mhard-mul -mhard-div -mror" - linker_output_format = "elf32-or1k" + @property + def name(self): + return "or1k" + + @property + def endianness(self): + return "big" + + @property + def gcc_triple(self): + return "or1k-elf" + + @property + def gcc_flags(self): + flags = "-mhard-mul " + flags += "-mhard-div " + flags += "-mror " + flags += "-D__mor1kx__ " + return flags + + @property + def clang_triple(self): + return "or1k-linux" + + @property + def clang_flags(self): + flags = "-mhard-mul " + flags += "-mhard-div " + flags += "-mror " + flags += "-mffl1 " + flags += "-maddc " + flags += "-D__mor1kx__ " + return flags + + @property + def linker_output_format(self): + return "elf32-or1k" def __init__(self, platform, reset_pc, variant="standard"): - assert variant in ("standard", "linux"), "Unsupported variant %s" % variant + assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant + self.platform = platform + self.variant = variant self.reset = Signal() self.ibus = i = wishbone.Interface() self.dbus = d = wishbone.Interface() @@ -48,12 +84,7 @@ class MOR1KX(Module): p_DBUS_WB_TYPE="B3_REGISTERED_FEEDBACK", ) - if variant == "standard": - # Use the default configuration - pass - elif variant == "linux": - self.clang_triple = "or1k-linux" - self.clang_flags = "-mhard-mul -mhard-div -mror -mffl1 -maddc" + if variant == "linux": cpu_args.update(dict( # Linux needs the memory management units. p_FEATURE_IMMU="ENABLED", @@ -70,9 +101,6 @@ class MOR1KX(Module): for to_remove in use_defaults: del cpu_args[to_remove] - else: - assert False, "Unsupported variant %s" % variant - i_adr_o = Signal(32) d_adr_o = Signal(32) self.specials += Instance("mor1kx", diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py index e2f32393..846ab07d 100644 --- a/litex/soc/cores/cpu/picorv32/core.py +++ b/litex/soc/cores/cpu/picorv32/core.py @@ -6,16 +6,49 @@ from migen import * from litex.soc.interconnect import wishbone +CPU_VARIANTS = ["minimal", "standard"] + +GCC_FLAGS = { + # /-------- Base ISA + # |/------- Hardware Multiply + Divide + # ||/----- Atomics + # |||/---- Compressed ISA + # ||||/--- Single-Precision Floating-Point + # |||||/-- Double-Precision Floating-Point + # imacfd + "minimal": "-march=rv32i -mabi=ilp32 ", + "standard": "-march=rv32im -mabi=ilp32 ", +} + + class PicoRV32(Module): - name = "picorv32" - endianness = "little" - gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf") - gcc_flags_template = "-D__picorv32__ -mno-save-restore -march=rv32{ext} -mabi=ilp32" - linker_output_format = "elf32-littleriscv" + @property + def name(self): + return "picorv32" - def __init__(self, platform, progaddr_reset, variant="standard"): - self.gcc_flags = "" + @property + def endianness(self): + return "little" + @property + def gcc_triple(self): + return ("riscv64-unknown-elf", "riscv32-unknown-elf") + + @property + def gcc_flags(self): + flags = "-mno-save-restore " + flags += GCC_FLAGS[self.variant] + flags += "-D__picorv32__ " + return flags + + @property + def linker_output_format(self): + return "elf32-littleriscv" + + def __init__(self, platform, progaddr_reset, variant="standard"): + assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant + self.platform = platform + self.variant = variant self.reset = Signal() self.ibus = i = wishbone.Interface() self.dbus = d = wishbone.Interface() @@ -62,9 +95,7 @@ class PicoRV32(Module): "p_STACKADDR" : 0xffffffff } - if variant == "standard": - self.gcc_flags = PicoRV32.gcc_flags_template.format(ext="im") - elif variant == "minimal": + if variant == "minimal": picorv32_params.update({ "p_ENABLE_COUNTERS" : 0, "p_ENABLE_COUNTERS64" : 0, @@ -74,7 +105,6 @@ class PicoRV32(Module): "p_ENABLE_DIV" : 0, "p_ENABLE_IRQ_TIMER" : 0 }) - self.gcc_flags = PicoRV32.gcc_flags_template.format(ext="i") self.specials += Instance("picorv32", # parameters dictionary diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index 1effc485..884915ae 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -33,24 +33,37 @@ GCC_FLAGS = { "lite+debug": "-march=rv32i -mabi=ilp32", "standard": "-march=rv32im -mabi=ilp32", "standard+debug": "-march=rv32im -mabi=ilp32", - # Does full have floating point? - Add -march=fd, and -mabi=fd - "full": "-march=rv32imac -mabi=ilp32", - "full+debug": "-march=rv32imac -mabi=ilp32", + "full": "-march=rv32im -mabi=ilp32", + "full+debug": "-march=rv32im -mabi=ilp32", "linux": "-march=rv32imac -mabi=ilp32", } class VexRiscv(Module, AutoCSR): - name = "vexriscv" - endianness = "little" - gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf") - linker_output_format = "elf32-littleriscv" + @property + def name(self): + return "vexriscv" - def __init__(self, platform, cpu_reset_address, variant="standard"): - assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant + @property + def endianness(self): + return "little" + + @property + def gcc_triple(self): + return ("riscv64-unknown-elf", "riscv32-unknown-elf") - self.gcc_flags = GCC_FLAGS[variant] + " -D__vexriscv__" + @property + def gcc_flags(self): + flags = GCC_FLAGS[self.variant] + flags += " -D__vexriscv__" + return flags + @property + def linker_output_format(self): + return "elf32-littleriscv" + + def __init__(self, platform, cpu_reset_address, variant="standard"): + assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant self.platform = platform self.variant = variant self.external_variant = None