From: Eddie Hung Date: Thu, 27 Jun 2019 03:07:31 +0000 (-0700) Subject: Merge remote-tracking branch 'origin/xaig' into xc7mux X-Git-Tag: working-ls180~1208^2~56 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dbb8c8caaa50d83c12665b7cfd11d79e8af06196;p=yosys.git Merge remote-tracking branch 'origin/xaig' into xc7mux --- dbb8c8caaa50d83c12665b7cfd11d79e8af06196 diff --cc techlibs/xilinx/abc_xc7.box index b1c24ed24,6dd71d758..7fe8a7236 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@@ -23,9 -18,10 +23,10 @@@ MUXF78 3 1 6 # Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI # Outputs: O0 O1 O2 O3 CO0 CO1 CO2 CO3 # (NB: carry chain input/output must be last - # input/output and have been moved there - # overriding the alphabetical ordering) + # input/output and the entire bus has been + # moved there overriding the otherwise + # alphabetical ordering) -CARRY4 3 1 10 8 +CARRY4 4 1 10 8 482 - - - - 223 - - - 222 598 407 - - - 400 205 - - 334 584 556 537 - - 523 558 226 - 239 diff --cc techlibs/xilinx/cells_sim.v index 354e4edbf,4ecf8277b..4a1e334d6 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@@ -289,7 -281,7 +289,7 @@@ module FDPE_1 (output reg Q, input C, C always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule - (* abc_box_id = 5, abc_scc_break="D" *) -(* abc_box_id = 4, abc_scc_break="D,WE" *) ++(* abc_box_id = 5, abc_scc_break="D,WE" *) module RAM32X1D ( output DPO, SPO, input D, WCLK, WE, @@@ -307,7 -299,7 +307,7 @@@ always @(posedge clk) if (WE) mem[a] <= D; endmodule - (* abc_box_id = 6, abc_scc_break="D" *) -(* abc_box_id = 5, abc_scc_break="D,WE" *) ++(* abc_box_id = 6, abc_scc_break="D,WE" *) module RAM64X1D ( output DPO, SPO, input D, WCLK, WE, @@@ -325,7 -317,7 +325,7 @@@ always @(posedge clk) if (WE) mem[a] <= D; endmodule - (* abc_box_id = 7, abc_scc_break="D" *) -(* abc_box_id = 6, abc_scc_break="D,WE" *) ++(* abc_box_id = 7, abc_scc_break="D,WE" *) module RAM128X1D ( output DPO, SPO, input D, WCLK, WE,