From: Tobias Platen <tplaten@posteo.de>
Date: Thu, 31 Mar 2022 18:46:21 +0000 (+0200)
Subject: building microwatt-verilator with external core now works
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dbb95b21c1c10ddcd4a88aaeed2cdb38e8b6cad5;p=microwatt.git

building microwatt-verilator with external core now works
---

diff --git a/Makefile b/Makefile
index 509cfdb..b061ddb 100644
--- a/Makefile
+++ b/Makefile
@@ -226,7 +226,7 @@ endif
 
  GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
 	-gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY) -gICACHE_NUM_LINES=$(ICACHE_NUM_LINES) \
-	$(LITEDRAM_GHDL_ARG) -gEXTERNAL_CORE=$(EXTERNAL_CORE)
+	$(LITEDRAM_GHDL_ARG) -gEXTERNAL_CORE=true #-gEXTERNAL_CORE=$(EXTERNAL_CORE)
 	
 #GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
 #	-gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY) \
@@ -280,6 +280,9 @@ microwatt-verilator-broken: microwatt.v verilator/microwatt-verilator.cpp verila
 	@cp -f obj_dir/microwatt-verilator microwatt-verilator
 	
 microwatt.v: $(synth_files) $(RAM_INIT_FILE)
+	$(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
+	
+microwatt.v.old: $(synth_files) $(RAM_INIT_FILE)
 	$(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
 	
 	
diff --git a/fpga/top-generic.vhdl b/fpga/top-generic.vhdl
index b0005ae..1da6b3f 100644
--- a/fpga/top-generic.vhdl
+++ b/fpga/top-generic.vhdl
@@ -11,6 +11,7 @@ entity toplevel is
 	RAM_INIT_FILE : string   := "firmware.hex";
 	RESET_LOW     : boolean  := true;
 	SIM_MAIN_BRAM     : boolean  := false;
+	EXTERNAL_CORE     : boolean  := false;
 	CLK_INPUT     : positive := 100000000;
 	CLK_FREQUENCY : positive := 100000000;
         HAS_FPU       : boolean  := true;
@@ -84,6 +85,7 @@ begin
 	    RAM_INIT_FILE => RAM_INIT_FILE,
 	    SIM           => false,
 	    CLK_FREQ      => CLK_FREQUENCY,
+	    EXTERNAL_CORE   => EXTERNAL_CORE,
             HAS_FPU       => HAS_FPU,
             HAS_BTC       => HAS_BTC,
             HAS_SHORT_MULT => HAS_SHORT_MULT,
diff --git a/soc.vhdl b/soc.vhdl
index 77d6456..65f535f 100644
--- a/soc.vhdl
+++ b/soc.vhdl
@@ -434,7 +434,7 @@ begin
 	    dmi_ack => dmi_core_ack,
 	    dmi_req => dmi_core_req,
 	    ext_irq => core_ext_irq, --LZ
-	    nia_req           => nia_req,
+	    nia_req           => nia_req, --FIXME: only when not using extcore
         nia               => nia,
         msr_o             => msr_o,
         insn              => insn,