From: lkcl <lkcl@web>
Date: Sun, 27 Jun 2021 04:21:48 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~715
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dbbb342e4debaca3bb6264efce84e4bcd0c88b4e;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 16615872e..baacec2d5 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -215,6 +215,10 @@ Note that cache-inhibited LD/ST (`ldcix`) when VSPLAT is activated will perform
 If a genuine cache-inhibited LD-VSPLAT is required then a *scalar*
 cache-inhibited LD should be performed, followed by a VSPLAT-augmented mv.
 
+## LD/ST ffirst
+
+ffirst LD/ST to multiple pages via a Vectorised base is considered a security risk due to the abuse of probing multiple pages in rapid succession and getting feedback on which pages would fail.  Therefore in these special circumstances requesting ffirst with a vector base is instead interpreted as element-strided LD/ST.  See <https://bugs.libre-soc.org/show_bug.cgi?id=561>
+
 # LOAD/STORE Elwidths <a name="ldst"></a>
 
 Loads and Stores are almost unique in that the OpenPOWER Scalar ISA