From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 9 Jun 2021 13:41:10 +0000 (+0100)
Subject: add PLL clock loop-back into CPU
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dbc42a5cf0453f5e9f7f0ec2a042f785c48e2a4a;p=libresoc-litex.git

add PLL clock loop-back into CPU
---

diff --git a/libresoc/core.py b/libresoc/core.py
index 6c39cd9..178ebe8 100644
--- a/libresoc/core.py
+++ b/libresoc/core.py
@@ -276,9 +276,11 @@ class LibreSoC(CPU):
             self.pll_vco_o = Signal()
             self.clk_sel = Signal(2)
             self.pll_test_o = Signal()
+            self.pllclk_o = Signal()
             self.cpu_params['i_clk_sel_i'] = self.clk_sel
             self.cpu_params['o_pll_vco_o'] = self.pll_vco_o
             self.cpu_params['o_pll_test_o'] = self.pll_test_o
+            self.cpu_params['o_pllclk_o'] = self.pllclk_o
 
         # add wishbone buses to cpu params
         self.cpu_params.update(make_wb_bus("ibus", ibus, True))
diff --git a/ls180soc.py b/ls180soc.py
index 6321b01..a240839 100755
--- a/ls180soc.py
+++ b/ls180soc.py
@@ -433,6 +433,7 @@ class LibreSoCSim(SoCCore):
             self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select
             self.comb += pll_test_o.eq(self.cpu.pll_test_o) # "test" from PLL
             self.comb += pll_vco_o.eq(self.cpu.pll_vco_o) # PLL lock flag
+            self.comb += self.cpu.clk.eq(self.cpu.pllclk_o) # PLL out into cpu
 
         #ram_init = []