From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 17 Jun 2020 17:31:40 +0000 (+0100)
Subject: add comment/assembly decode in power enums
X-Git-Tag: div_pipeline~336
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dbd12c2c042793cb5a73d856b73cc94123ff5890;p=soc.git

add comment/assembly decode in power enums
---

diff --git a/src/soc/decoder/power_decoder.py b/src/soc/decoder/power_decoder.py
index 69292429..0b9ffc5b 100644
--- a/src/soc/decoder/power_decoder.py
+++ b/src/soc/decoder/power_decoder.py
@@ -87,7 +87,7 @@ from soc.decoder.power_enums import (Function, Form, InternalOp,
                                      RC, LdstLen, CryIn, get_csv,
                                      single_bit_flags, CRInSel,
                                      CROutSel, get_signal_name,
-                                     default_values)
+                                     default_values, insns, asmidx)
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SigDecode, SignalBitRange
 
@@ -115,10 +115,12 @@ class PowerOp:
     is Decode2ToExecute1Type
     """
 
-    def __init__(self):
+    def __init__(self, incl_asm=True):
         self.function_unit = Signal(Function, reset_less=True)
         self.internal_op = Signal(InternalOp, reset_less=True)
         self.form = Signal(Form, reset_less=True)
+        if incl_asm: # for simulator only
+            self.asmcode = Signal(7, reset_less=True)
         self.in1_sel = Signal(In1Sel, reset_less=True)
         self.in2_sel = Signal(In2Sel, reset_less=True)
         self.in3_sel = Signal(In3Sel, reset_less=True)
@@ -144,6 +146,7 @@ class PowerOp:
         if row['CR out'] == '0':
             import pdb; pdb.set_trace()
             print(row)
+        print(row)
         res = [self.function_unit.eq(Function[row['unit']]),
                self.form.eq(Form[row['form']]),
                self.internal_op.eq(InternalOp[row['internal op']]),
@@ -157,6 +160,9 @@ class PowerOp:
                self.rc_sel.eq(RC[row['rc']]),
                self.cry_in.eq(CryIn[row['cry in']]),
                ]
+        print (row.keys())
+        if hasattr(self, "asmcode"):
+            res.append(self.asmcode.eq(asmidx[row['comment']]))
         for bit in single_bit_flags:
             sig = getattr(self, get_signal_name(bit))
             res.append(sig.eq(int(row.get(bit, 0))))
@@ -178,6 +184,8 @@ class PowerOp:
         for bit in single_bit_flags:
             sig = getattr(self, get_signal_name(bit))
             res.append(sig.eq(getattr(otherop, get_signal_name(bit))))
+        if hasattr(self, "asmcode"):
+            res.append(self.asmcode.eq(otherop.asmcode))
         return res
 
     def ports(self):
diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index 9170359f..5d0b8eb0 100644
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -89,6 +89,44 @@ class Form(Enum):
     Z22 = 27
     Z23 = 28
 
+# supported instructions: make sure to keep up-to-date with CSV files
+# just like everything else
+_insns = [
+    "add", "addc", "addco", "adde", "addeo", "addi", "addic", "addic.",
+    "addis", "addme", "addmeo", "addo", "addze", "addzeo", "and", "andc",
+    "andi.", "andis.", "attn", "b", "bc", "bcctr", "bclr", "bctar",
+    "bperm", "cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
+    "cntlzd", "cntlzw", "cnttzd", "cnttzw", "crand", "crandc", "creqv",
+    "crnand", "crnor", "cror", "crorc", "crxor", "darn", "dcbf", "dcbst",
+    "dcbt", "dcbtst", "dcbz", "divd", "divde", "divdeo", "divdeu",
+    "divdeuo", "divdo", "divdu", "divduo", "divw", "divwe", "divweo",
+    "divweu", "divweuo", "divwo", "divwu", "divwuo", "eqv", "extsb",
+    "extsh", "extsw", "extswsli", "icbi", "icbt", "isel", "isync",
+    "lbarx", "lbz", "lbzu", "lbzux", "lbzx", "ld", "ldarx", "ldbrx",
+    "ldu", "ldux", "ldx", "lha", "lharx", "lhau", "lhaux", "lhax",
+    "lhbrx", "lhz", "lhzu", "lhzux", "lhzx", "lwa", "lwarx", "lwaux",
+    "lwax", "lwbrx", "lwz", "lwzu", "lwzux", "lwzx", "mcrf", "mcrxr",
+    "mcrxrx", "mfcr/mfocrf", "mfmsr", "mfspr", "modsd", "modsw", "modud",
+    "moduw", "mtcrf/mtocrf", "mtmsrd", "mtspr", "mulhd", "mulhdu",
+    "mulhw", "mulhwu", "mulld", "mulldo", "mulli", "mullw", "mullwo",
+    "nand", "neg", "nego", "nop", "nor", "or", "orc", "ori", "oris",
+    "popcntb", "popcntd", "popcntw", "prtyd", "prtyw", "rfid", "rldcl",
+    "rldcr", "rldic", "rldicl", "rldicr", "rldimi", "rlwimi", "rlwinm",
+    "rlwnm", "setb", "sim_cfg", "sld", "slw", "srad", "sradi", "sraw",
+    "srawi", "srd", "srw", "stb", "stbcx", "stbu", "stbux", "stbx", "std",
+    "stdbrx", "stdcx", "stdu", "stdux", "stdx", "sth", "sthbrx", "sthcx",
+    "sthu", "sthux", "sthx", "stw", "stwbrx", "stwcx", "stwu", "stwux",
+    "stwx", "subf", "subfc", "subfco", "subfe", "subfeo", "subfic",
+    "subfme", "subfmeo", "subfo", "subfze", "subfzeo", "sync", "td",
+    "tdi", "tw", "twi", "xor", "xori", "xoris",
+]
+
+# two-way lookup of instruction-to-index and vice-versa
+insns = {}
+asmidx = {}
+for i, insn in enumerate(_insns):
+    insns[i] = insn
+    asmidx[insn] = i
 
 # Internal Operation numbering.  Add new opcodes here (FPADD, FPMUL etc.)
 @unique