From: Marcelina Koƛcielnicka Date: Tue, 21 Jul 2020 13:00:54 +0000 (+0200) Subject: techmap: Add _TECHMAP_CELLNAME_ special parameter. X-Git-Tag: working-ls180~365^2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dc07ae96774c649d23ea787e07d618670c7e93bf;p=yosys.git techmap: Add _TECHMAP_CELLNAME_ special parameter. This parameter will resolve to the name of the cell being mapped. The first user of this parameter will be synth_intel_alm's Quartus output, which requires a unique (and preferably descriptive) name passed as a cell parameter for the memory cells. --- diff --git a/CHANGELOG b/CHANGELOG index 12fc88550..08af3f4c9 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -39,7 +39,7 @@ Yosys 0.9 .. Yosys 0.9-dev - Improvements in pmgen: slices, choices, define, generate - Added "xilinx_srl" for Xilinx shift register extraction - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl") - - Added "_TECHMAP_WIREINIT_*_" attribute and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass + - Added "_TECHMAP_WIREINIT_*_" parameter and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass - Added "-match-init" option to "dff2dffs" pass - Added "techmap_autopurge" support to techmap - Added "add -mod " @@ -69,6 +69,7 @@ Yosys 0.9 .. Yosys 0.9-dev - Added $divfloor and $modfloor cells - Added $adffe, $dffsre, $sdff, $sdffe, $sdffce, $adlatch cells - Added "dfflegalize" pass + - Added "_TECHMAP_CELLNAME_" parameter for "techmap" pass Yosys 0.8 .. Yosys 0.9 ---------------------- diff --git a/kernel/constids.inc b/kernel/constids.inc index 69bc06d2c..3c2ff9beb 100644 --- a/kernel/constids.inc +++ b/kernel/constids.inc @@ -172,6 +172,7 @@ X(T) X(TABLE) X(techmap_autopurge) X(_TECHMAP_BITS_CONNMAP_) +X(_TECHMAP_CELLNAME_) X(_TECHMAP_CELLTYPE_) X(techmap_celltype) X(_TECHMAP_FAIL_) diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index f98d1564a..8e6630c89 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -643,6 +643,8 @@ struct TechmapWorker if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0) parameters.emplace(ID::_TECHMAP_CELLTYPE_, RTLIL::unescape_id(cell->type)); + if (tpl->avail_parameters.count(ID::_TECHMAP_CELLNAME_) != 0) + parameters.emplace(ID::_TECHMAP_CELLNAME_, RTLIL::unescape_id(cell->name)); for (auto &conn : cell->connections()) { if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first))) != 0) { @@ -1111,6 +1113,10 @@ struct TechmapPass : public Pass { log(" When a parameter with this name exists, it will be set to the type name\n"); log(" of the cell that matches the module.\n"); log("\n"); + log(" _TECHMAP_CELLNAME_\n"); + log(" When a parameter with this name exists, it will be set to the name\n"); + log(" of the cell that matches the module.\n"); + log("\n"); log(" _TECHMAP_CONSTMSK__\n"); log(" _TECHMAP_CONSTVAL__\n"); log(" When this pair of parameters is available in a module for a port, then\n"); diff --git a/tests/techmap/cellname.ys b/tests/techmap/cellname.ys new file mode 100644 index 000000000..2edd6a9fd --- /dev/null +++ b/tests/techmap/cellname.ys @@ -0,0 +1,41 @@ +read_verilog << EOT + +module sub (input i, output o); +parameter _TECHMAP_CELLNAME_ = ""; +namedsub #(.name(_TECHMAP_CELLNAME_)) _TECHMAP_REPLACE_ (i, o); +endmodule + +EOT + +design -stash map + +read_verilog << EOT + +(* blackbox *) +module sub (input i, output o); +endmodule + +(* blackbox *) +module namedsub (input i, output o); +parameter name = ""; +endmodule + +module top(input [3:0] i, output [3:0] o); + +sub s1 (i[0], o[0]); +sub subsubsub (i[1], o[1]); +sub s2 (i[2], o[2]); +sub xxx (i[3], o[3]); + +endmodule + +EOT + +techmap -map %map + +select -assert-count 4 t:namedsub +select -assert-count 0 t:sub +select -assert-count 1 t:namedsub r:name=s1 %i +select -assert-count 1 t:namedsub r:name=subsubsub %i +select -assert-count 1 t:namedsub r:name=s2 %i +select -assert-count 1 t:namedsub r:name=xxx %i