From: lkcl <lkcl@web>
Date: Sat, 26 Dec 2020 17:01:37 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~844
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dc1f7d3889484616d1783d3e41681be46525079b;p=libreriscv.git

---

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index 9fd9884cc..12f80db61 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -63,7 +63,7 @@ Hardware (and simulator) implementors are free and clear to implement this
 as literally a for-loop, sitting in between instruction decode and issue.
 Higher performance systems may deploy SIMD backends, multi-issue and
 out-of-order execution, although it is strongly recommended to add
-predication capability into all SIMD backend units.
+predication capability directly into SIMD backend units.
 
 In OpenPOWER ISA v3.0B pseudo-code form, an ADD operation, assuming both
 source and destination have been "tagged" as Vectors, is simply: