From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 3 Jun 2020 12:35:08 +0000 (+0100)
Subject: use common get_cu_inputs for CR unit tests
X-Git-Tag: div_pipeline~636^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dc205e61905f3bb647bde7245ec63be4db4b10be;p=soc.git

use common get_cu_inputs for CR unit tests
---

diff --git a/src/soc/fu/compunits/test/test_cr_compunit.py b/src/soc/fu/compunits/test/test_cr_compunit.py
index 5d502f9f..47e32e02 100644
--- a/src/soc/fu/compunits/test/test_cr_compunit.py
+++ b/src/soc/fu/compunits/test/test_cr_compunit.py
@@ -2,6 +2,7 @@ import unittest
 from soc.decoder.power_enums import (XER_bits, Function)
 
 # XXX bad practice: use of global variables
+from soc.fu.cr.test.test_pipe_caller import get_cu_inputs
 from soc.fu.cr.test.test_pipe_caller import CRTestCase
 from soc.fu.cr.test.test_pipe_caller import test_data
 
@@ -17,43 +18,7 @@ class CRTestRunner(TestRunner):
     def get_cu_inputs(self, dec2, sim):
         """naming (res) must conform to CRFunctionUnit input regspec
         """
-        res = {}
-        full_reg = yield dec2.e.read_cr_whole
-
-        # full CR
-        print(sim.cr.get_range().value)
-        if full_reg:
-            res['full_cr'] = sim.cr.get_range().value
-        else:
-            # CR A
-            cr1_en = yield dec2.e.read_cr1.ok
-            if cr1_en:
-                cr1_sel = yield dec2.e.read_cr1.data
-                res['cr_a'] = sim.crl[cr1_sel].get_range().value
-            cr2_en = yield dec2.e.read_cr2.ok
-            # CR B
-            if cr2_en:
-                cr2_sel = yield dec2.e.read_cr2.data
-                res['cr_b'] = sim.crl[cr2_sel].get_range().value
-            cr3_en = yield dec2.e.read_cr3.ok
-            # CR C
-            if cr3_en:
-                cr3_sel = yield dec2.e.read_cr3.data
-                res['cr_c'] = sim.crl[cr3_sel].get_range().value
-
-        # RA/RC
-        reg1_ok = yield dec2.e.read_reg1.ok
-        if reg1_ok:
-            data1 = yield dec2.e.read_reg1.data
-            res['ra'] = sim.gpr(data1).value
-
-        # RB (or immediate)
-        reg2_ok = yield dec2.e.read_reg2.ok
-        if reg2_ok:
-            data2 = yield dec2.e.read_reg2.data
-            res['rb'] = sim.gpr(data2).value
-
-        print ("get inputs", res)
+        res = yield from get_cu_inputs(dec2, sim)
         return res
 
     def check_cu_outputs(self, res, dec2, sim, code):
diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py
index ffe6bad5..b67ed831 100644
--- a/src/soc/fu/cr/test/test_pipe_caller.py
+++ b/src/soc/fu/cr/test/test_pipe_caller.py
@@ -141,44 +141,74 @@ class CRTestCase(FHDLTestCase):
             f.write(vl)
 
 
+def get_cu_inputs(dec2, sim):
+    """naming (res) must conform to CRFunctionUnit input regspec
+    """
+    res = {}
+    full_reg = yield dec2.e.read_cr_whole
+
+    # full CR
+    print(sim.cr.get_range().value)
+    if full_reg:
+        res['full_cr'] = sim.cr.get_range().value
+    else:
+        # CR A
+        cr1_en = yield dec2.e.read_cr1.ok
+        if cr1_en:
+            cr1_sel = yield dec2.e.read_cr1.data
+            res['cr_a'] = sim.crl[cr1_sel].get_range().value
+        cr2_en = yield dec2.e.read_cr2.ok
+        # CR B
+        if cr2_en:
+            cr2_sel = yield dec2.e.read_cr2.data
+            res['cr_b'] = sim.crl[cr2_sel].get_range().value
+        cr3_en = yield dec2.e.read_cr3.ok
+        # CR C
+        if cr3_en:
+            cr3_sel = yield dec2.e.read_cr3.data
+            res['cr_c'] = sim.crl[cr3_sel].get_range().value
+
+    # RA/RC
+    reg1_ok = yield dec2.e.read_reg1.ok
+    if reg1_ok:
+        data1 = yield dec2.e.read_reg1.data
+        res['ra'] = sim.gpr(data1).value
+
+    # RB (or immediate)
+    reg2_ok = yield dec2.e.read_reg2.ok
+    if reg2_ok:
+        data2 = yield dec2.e.read_reg2.data
+        res['rb'] = sim.gpr(data2).value
+
+    print ("get inputs", res)
+    return res
+
+
 class TestRunner(FHDLTestCase):
     def __init__(self, test_data):
         super().__init__("run_all")
         self.test_data = test_data
 
     def set_inputs(self, alu, dec2, simulator):
-        full_reg = yield dec2.e.read_cr_whole
-
-        print(simulator.cr.get_range().value)
-        if full_reg:
-            yield alu.p.data_i.full_cr.eq(simulator.cr.get_range().value)
+        inp = yield from get_cu_inputs(dec2, simulator)
+        if 'full_cr' in inp:
+            yield alu.p.data_i.full_cr.eq(inp['full_cr'])
+        else:
+            yield alu.p.data_i.full_cr.eq(0)
+        if 'cr_a' in inp:
+            yield alu.p.data_i.cr_a.eq(inp['cr_a'])
+        if 'cr_b' in inp:
+            yield alu.p.data_i.cr_b.eq(inp['cr_b'])
+        if 'cr_c' in inp:
+            yield alu.p.data_i.cr_c.eq(inp['cr_c'])
+        if 'ra' in inp:
+            yield alu.p.data_i.ra.eq(inp['ra'])
+        else:
+            yield alu.p.data_i.ra.eq(0)
+        if 'rb' in inp:
+            yield alu.p.data_i.rb.eq(inp['rb'])
         else:
-            cr1_en = yield dec2.e.read_cr1.ok
-            if cr1_en:
-                cr1_sel = yield dec2.e.read_cr1.data
-                cr1 = simulator.crl[cr1_sel].get_range().value
-                yield alu.p.data_i.cr_a.eq(cr1)
-            cr2_en = yield dec2.e.read_cr2.ok
-            if cr2_en:
-                cr2_sel = yield dec2.e.read_cr2.data
-                cr2 = simulator.crl[cr2_sel].get_range().value
-                yield alu.p.data_i.cr_b.eq(cr2)
-            cr3_en = yield dec2.e.read_cr3.ok
-            if cr3_en:
-                cr3_sel = yield dec2.e.read_cr3.data
-                cr3 = simulator.crl[cr3_sel].get_range().value
-                yield alu.p.data_i.cr_c.eq(cr3)
-
-        reg1_ok = yield dec2.e.read_reg1.ok
-        if reg1_ok:
-            reg1_sel = yield dec2.e.read_reg1.data
-            reg1 = simulator.gpr(reg1_sel).value
-            yield alu.p.data_i.a.eq(reg1)
-        reg2_ok = yield dec2.e.read_reg2.ok
-        if reg2_ok:
-            reg2_sel = yield dec2.e.read_reg2.data
-            reg2 = simulator.gpr(reg2_sel).value
-            yield alu.p.data_i.b.eq(reg2)
+            yield alu.p.data_i.rb.eq(0)
 
     def assert_outputs(self, alu, dec2, simulator, code):
         whole_reg = yield dec2.e.write_cr_whole