From: whitequark <whitequark@whitequark.org>
Date: Thu, 9 Jul 2020 19:36:39 +0000 (+0000)
Subject: verilog_parser: turn S/R and R/R conflicts into hard errors.
X-Git-Tag: working-ls180~391^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dc35ef05f93bf634e7f158869af48707233505e2;p=yosys.git

verilog_parser: turn S/R and R/R conflicts into hard errors.

Fixes #2253.
---

diff --git a/frontends/verilog/Makefile.inc b/frontends/verilog/Makefile.inc
index cf9b9531e..d5d5edd3d 100644
--- a/frontends/verilog/Makefile.inc
+++ b/frontends/verilog/Makefile.inc
@@ -6,7 +6,7 @@ GENFILES += frontends/verilog/verilog_lexer.cc
 
 frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y
 	$(Q) mkdir -p $(dir $@)
-	$(P) $(BISON) -o $@ -d -r all -b frontends/verilog/verilog_parser $<
+	$(P) $(BISON) -Werror=conflicts-sr,error=conflicts-rr -o $@ -d -r all -b frontends/verilog/verilog_parser $<
 
 frontends/verilog/verilog_parser.tab.hh: frontends/verilog/verilog_parser.tab.cc