From: lkcl <lkcl@web>
Date: Mon, 4 Jul 2022 16:39:11 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1328
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dc371890234e2380d55f18f872ebd8fe975e9fd7;p=libreriscv.git

---

diff --git a/3d_gpu/layouts/coriolis2_180nm.mdwn b/3d_gpu/layouts/coriolis2_180nm.mdwn
index f5b48c696..c6f67ec9a 100644
--- a/3d_gpu/layouts/coriolis2_180nm.mdwn
+++ b/3d_gpu/layouts/coriolis2_180nm.mdwn
@@ -6,8 +6,6 @@
 * <https://ftp.libre-soc.org/course_18oct2021>
 * [[180nm_Oct2020]]
 
-<img src="https://ftp.libre-soc.org/course_18oct2021/drawing-2.svg" width=500 />
-
 # Simple floorplan
 
 [[!img simple_floorplan.png size="500x"]]
@@ -113,3 +111,11 @@ These included:
 
 Overall it was a significant amount of work and it is entirely
 automated `RTL2GDS`, no manual intervention required.
+
+<img src="https://ftp.libre-soc.org/course_18oct2021/drawing-2.svg" width=500 />
+
+coriolis2 converts verilog to BLIF using yosys and the Cell Library, then converts
+BLIF into a VHDL subset.  This subset is extremely simple, comprising
+links (netlists) to cells and nothing more. It can be extracted and
+converted to actual VHDL and substituted successfully into verilator,
+ghdl or icarus simulations using cocotb (caveat: the files are enormous).