From: Ron Dreslinski <rdreslin@umich.edu>
Date: Tue, 15 Aug 2006 18:24:49 +0000 (-0400)
Subject: Some changes to support blocking in the caches
X-Git-Tag: m5_2.0_beta1~36^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dc375e42bc739e8869a75993a93ed8afc3f294cc;p=gem5.git

Some changes to support blocking in the caches

src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache_impl.hh:
    Outstanding blocking updates for cache

--HG--
extra : convert_revision : 3a7b4aa4921de8239f604f1852f262a2305862c0
---

diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 451da28e8..9b1034577 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -71,6 +71,11 @@ BaseCache::CachePort::deviceBlockSize()
 bool
 BaseCache::CachePort::recvTiming(Packet *pkt)
 {
+    if (blocked)
+    {
+        mustSendRetry = true;
+        return false;
+    }
     return cache->doTimingAccess(pkt, this, isCpuSide);
 }
 
@@ -95,6 +100,11 @@ BaseCache::CachePort::setBlocked()
 void
 BaseCache::CachePort::clearBlocked()
 {
+    if (mustSendRetry)
+    {
+        mustSendRetry = false;
+        sendRetry();
+    }
     blocked = false;
 }
 
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 0d1bfdfdb..823465769 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -105,6 +105,8 @@ class BaseCache : public MemObject
 
         bool blocked;
 
+        bool mustSendRetry;
+
         bool isCpuSide;
     };
 
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index a447ae3d5..db012920f 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -71,7 +71,7 @@ doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
         else
             snoop(pkt);
     }
-    return true; //Deal with blocking....
+    return true;
 }
 
 template<class TagStore, class Buffering, class Coherence>